Using clock and data recovery phase adjust to set loop delay of a decision feedback equalizer

A communication system comprising:

• a transmitter transmitting an information signal over a communication media;
• and
• a receiver coupled to the communication media for receiving the transmitted information signal, wherein the receiver comprises:
• a decision feedback equalizer adapted to reduce channel related distortion in received data, wherein the decision feedback equalizer is configured to generate equalized data;
• and
• a clock and data recovery circuit coupled to the equalizer, the clock and data recovery circuit configured to generate an extracted clock signal,
• wherein the clock and data recovery circuit is configured to adjust a phase of the extracted clock signal relative to the equalized data to compensate for processing delays in the decision feedback equalizer, and
• wherein the decision feedback equalizer includes a retimer that is configured to generate recovered equalized data from the equalized data in response to the extracted clock signal.

A communications system comprising:

• a decision feedback equalizer adapted to reduce channel related distortion in received data, the decision feedback equalizer comprising:
• a summer that is configured to combine an equalized feedback signal with the received data,
• a slicer coupled to the summer, the slicer being configured to convert the combined signal to a binary signal;
• a retimer coupled to the slicer, the retimer being configured to generate recovered equalized data from the binary signal in response to an extracted clock signal, and
• a multiplier coupled to the retimer, the multiplier being configured to apply an equalization coefficient to the recovered equalized data to generate the equalized feedback signal;
• and
• a clock and data recovery circuit coupled to the slicer, the clock and data recovery circuit being configured to generate the extracted clock signal from the binary signal, wherein the clock and data recovery circuit is configured to adjust phase of the extracted clock signal to compensate for processing delays in the decision feedback equalizer.

A communications system comprising:

• a decision feedback equalizer adapted to reduce channel related distortion in received data, wherein the decision feedback equalizer generates equalized data;
• and
• a clock and data recovery circuit coupled to the equalizer, wherein the clock and data recovery circuit is configured to generate an extracted clock signal from the equalized data, and wherein the decision feedback equalizer includes a retimer that is configured to generate recovered equalized data from the equalized data in response to the extracted clock signal;
• and
• a real time optimizer coupled to the clock and data recovery circuit, wherein the real time optimizer is configured to generate a phase adjust signal and wherein the clock and data recovery circuit is configured to adjust a phase of the extracted clock signal in response to the phase adjust signal to compensate for processing delays in the decision feedback equalizer.

A method comprising:

• providing received data to a decision feedback equalizer;
• generating, by the decision feedback equalizer, a binary signal according to the received data;
• generating a phase delay signal based on processing delays associated with the decision feedback equalizer;
• extracting a clock signal from the binary signal according to the phase delay signal, to thereby compensate for the processing delays;
• and
• retiming the binary signal according to the clock signal.