Asynchronous sample rate correction by time domain interpolation

A method of correcting a sample rate by

• receiving an input signal operating at a first frequency;
• transmitting the input signal into an up input of an up/down counter;
• transmitting an output signal from the up/down counter to a first input of an adder;
• transmitting output of the adder into a modulator, where the modulator is clocked at a second frequency, and wherein the modulator produces a modulator output that is fed back as a second input of the adder;
• and
• if an overflow occurs at the adder, transmitting a carry output from the adder that is fed back to a down input of the up/down counter to reset the up/down counter.

A circuit configured to correct sample rates by way of time domain interpolation, comprising:

• a first circuit loop having a first up/down counter configured to receive a first input signal at a first input frequency and a first feedback signal and a first adder configured to receive a first counter output signal from the first up/down counter and to output a first carry output as the first feedback signal to the first up/down counter;
• a second circuit loop configured to transmit a first sum output from the first adder to a first modulator and to feed back a first modulator output signal from the first modulator to a first input of the first adder, wherein the first modulator output signal has a first output frequency greater than the first input frequency;
• a third circuit loop having a second up/down counter configured to receive a second feedback signal and a second input signal at a second input frequency different from the first input frequency and a second adder configured to receive a second counter output signal from the second up/down counter and to output a second carry output as the second feedback signal to the second up/down counter;
• and
• a fourth circuit loop configured to transmit a second sum output from the second adder to a second modulator and to feed back a second modulator output signal from the second modulator to a second input of the second adder, wherein the second modulator output signal has the first output frequency greater than the second input frequency.

A method of correcting a sample rate by

• receiving a first input signal operating at a first input frequency;
• transmitting the first input signal into a first up input of a first up/down counter;
• transmitting a first output signal from the first up/down counter to a first input of a first adder;
• transmitting output of the first adder into a first modulator, where the first modulator is clocked at a first output frequency greater than the first input frequency, and wherein the first modulator produces a first modulator output that is fed back as a second input of the first adder;
• and
• if an overflow occurs at the first adder, transmitting a first carry output from the first adder that is fed back to a first down input of the first up/down counter to reset the first up/down counter;
• receiving a second input signal operating at a second input frequency;
• transmitting the second input signal into a second up input of a second up/down counter;
• transmitting a second output signal from the second up/down counter to a first input of a second adder;
• transmitting output of the second adder into a second modulator, where the second modulator is clocked at the first output frequency greater than the second input frequency, and wherein the second modulator produces a second modulator output that is fed back as a second input of the second adder;
• and
• if an overflow occurs at the second adder, transmitting a second carry output from the second adder that is fed back to a second down input of the second up/down counter to reset the second up/down counter.

A method, comprising:

• receiving a first input signal operating at a first input frequency;
• transmitting the first input signal into a first up input of a first up/down counter;
• transmitting a first output signal from the first up/down counter to a first input of a first adder;
• transmitting output of the first adder into a first modulator, where the first modulator is clocked at a first output frequency greater than the first input frequency, and wherein the first modulator produces a first modulator output that is fed back as a second input of the first adder;
• if an overflow occurs at the first adder, transmitting a first carry output from the first adder that is fed back to a first down input of the first up/down counter to reset the first up/down counter;
• and
• mixing the first modulator output having the first output frequency with a mixer input signal having the first output frequency, wherein the mixer input signal was processed from a second input signal having a second input frequency less than the first output frequency.