Error correction for programmable logic integrated circuits

A circuit that corrects errors in configuration data stored on a programmable logic device, the circuit comprising:

• a memory, incorporated in the programmable logic device, in which the configuration data and error check data associated with the configuration data are stored;
• and
• error correction circuitry coupled to at least some of the memory to analyze the configuration data stored in the memory to determine if any values have changed after initial configuration of the memory and to correct any values that have changed;
• wherein:
• each bit of the configuration data is stored in a first cell, a second cell, and a third cell in the memory.

A circuit that corrects errors in configuration data stored on a programmable logic device, the circuit comprising:

• a memory, incorporated in the programmable logic device, in which the configuration data and error check data associated with the configuration data are stored;
• error correction circuitry coupled to at least some of the memory to analyze the configuration data stored in the memory to determine if any values have changed after initial configuration of the memory and to correct any values that have changed;
• a resistive element coupled to an output of the error correction circuitry;
• and
• a capacitive load coupled to the resistive element, wherein the resistive element and the capacitive load are operative to reduce static hazards associated with the error correction circuitry.

A circuit that corrects errors in configuration data stored on a programmable logic device comprising:

• a memory array of representative rows and representative columns of cells in which the configuration data and error check data associated with the configuration data are stored;
• first circuitry having an input operative to receive data from each cell in a representative row of the array and an output, the first circuitry generating a first parity for the data in the representative row at the output;
• second circuitry having an input operative to receive data from each cell in a representative column of the array and an output, the second circuitry generating a second parity for the data in the representative column at the output;
• third circuitry having a first input operative to receive the output of the first circuitry, having a second input operative to receive the output of the second circuitry, and an output, the third circuitry sending a signal at the output indicative of whether an error has occurred in a cell in the representative row and the representative column based on the first parity and the second parity;
• and
• fourth circuitry having a first input operative to receive the output of the third circuitry, a second input operative to receive data from the cell in the representative row and the representative column, and an output, the fourth circuitry sending a signal at the output having a correct value.

A circuit that corrects errors in configuration data stored on a programmable logic device comprising:

• a memory array of representative rows and representative columns of cells in which the configuration data and error check data associated with the configuration data are stored;
• first circuitry having an input operative to receive data from all but one cell in a representative row of the array and an output, the first circuitry generating a first parity for the data from all but the one cell in the representative row at the output;
• second circuitry having an input operative to receive data from all but the one cell in a representative column of the array and an output, the second circuitry generating a second parity for the data from all but the one cell in the representative column at the output;
• and
• third circuitry having a first input operative to receive the output of the first circuitry, a second input operative to receive the output of the second circuitry, a third input operative to receive data from the one cell, and an output, the third circuitry generating a correct value at the output.

A method for correcting errors in configuration data stored on a programmable logic device comprising:

• generating error check data associated with the configuration data and storing the error check data in a memory, incorporated in the programmable logic device, in which the configuration data are stored;
• reading a portion of the configuration data and an associated portion of the error check data;
• determining if an error has occurred based on the portion of the configuration data and the associated portion of the error check data;
• and
• correcting the portion of the configuration data in response to the determining;
• wherein:
• the portion of the configuration data is at least two partial representative columns of cells in the memory that are physically non-contiguous.