Storage system comprising logical circuit configured in accordance with information in memory on PLD
AssigneeHitachi, Ltd.
InventorTakahiro Sasakura
Life of this patent
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Abstract
The storage system includes a PLD (Programmable Logic Device), which controls data transfer between another device and a media drive; and a processor. The PLD includes a memory for storing information input from an information source located externally to the PLD; a circuit element group including a plurality of circuit elements; and a logical circuit configured on the circuit element group in accordance with the information in the memory. The processor detects whether a soft error has occurred in the memory, detects whether or not an error has occurred in the logical circuit, and implements control in accordance with the results of the two detection operations.
Claims8
A storage system for transmitting data to and receiving data from other devices, said storage system comprising:
- a media drive that stores transmitted and received data;
- a PLD (Programmable Logic Device) for controlling data transfer between said other devices and said media drive;
- and
- a processor,
- wherein said PLD comprises:
- a memory for storing circuit configuration information indicating the configuration of a logical circuit, input from an information source located externally to said PLD,
- wherein if a soft error occurs in said memory, then said memory provides an interrupt signal to said processor;
- a circuit element group comprising a plurality of circuit elements;
- and
- a logical circuit for controlling said data transfer, configured on said circuit element group in accordance with the circuit configuration information in said memory,
- wherein said logical circuit comprises a plurality of subsidiary circuits and a plurality of error checking circuits, each of said plurality of subsidiary circuits including one of said plurality of error checking circuits, which check whether a hardware error has occurred in a corresponding subsidiary circuit, and
- wherein if at least one of said error checking circuits detects a hardware error, then an error report is stored, and
- wherein said processor:
- detects that said soft error has occurred in said memory if said interrupt signal is received by said processor from said memory;
- detects that said hardware error has occurred in said logical circuit if said error report is stored;
- and
- implements control based on which of said soft error and said hardware error the processor detects first.
A method for controlling a device having a PLD (Programmable Logic Device), said PLD comprising a memory for storing information input from an information source located externally to the PLD, a circuit element group comprising a plurality of circuit elements, and a logical circuit configured on said circuit element group in accordance with the information in said memory, wherein said method comprises:
- providing an interrupt signal to said processor if a soft error occurs in said memory;
- checking whether a hardware error has occurred in at least one subsidiary circuit of said logical circuit, and storing an error report if a hardware error is detected in at least one subsidiary circuit of said logical circuit;
- detecting that said soft error has occurred in said memory if said interrupt signal is received by said Processor;
- detecting that said hardware error has occurred in said logical circuit if said error report is stored;
- and
- implementing control based on which of said soft error and said hardware error the processor detects first.
A computer program to be executed by a computer having a PLD (Programmable Logic Device), said PLD comprising a memory for storing information input from an information source located externally to the PLD, a circuit element group comprising a plurality of circuit elements, and a logical circuit configured on said circuit element group in accordance with the information in said memory, wherein said computer program causes a processor to execute the steps of:
- providing an interrupt signal to said processor if a soft error occurs in said memory;
- checking whether a hardware error has occurred in at least one subsidiary circuit of said logical circuit, and storing an error report if a hardware error is detected in at least one subsidiary circuit of said logical circuit;
- detecting that said soft error has occurred in said memory if said interrupt signal is received by said processor;
- detecting that said hardware error has occurred in said logical circuit if said error report is stored;
- and
- implementing control based on which of said soft error and said hardware error the processor detects first.
Dependencies are inferred from the claim text.