Low power high density random access memory flash cells and arrays

A flash memory comprising:

• an array of rows and columns of floating gate memory cells, each memory cell having a source, a drain, a gate and a floating gate;
• the array including a global bit line and a global source line for each column of cells, the rows of cells being grouped in sectors, each sector including a predetermined number of rows, the drains of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global bit line through first access transistors, the sources of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global source line through second access transistors;
• the gates of the floating gate memory cells in each row of floating gate memory cells being connected to a respective word line;
• circuitry configured to controllably provide a voltage of a first polarity between the gate and the drain of one or more selected cells in a sector to program the selected cell by Fowler Nordheim tunneling and restricting voltages on floating gate memory cells not intended to be programmed to lesser voltages not disturbing the state of the floating gate memory cells not intended to be programmed;
• and,
• to controllably provide a voltage of a second polarity opposite the first polarity between the gate and the drain of one or more selected rows of cells to erase the selected rows of cells by Fowler Nordheim tunneling and for restricting voltages on floating gate memory cells not intended to be erased to lesser voltages not disturbing the programming of the floating gate memory cells not intended to be erased.

A low power program and erase flash memory method comprising:

• providing an array of rows and columns of floating gate memory cells, each memory cell having a source, a drain, a gate and a floating gate, the array including a global bit line and a global source line for each column of cells, the rows of cells being grouped in sectors, each sector including a predetermined number of rows, the drains of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global bit line through first access transistors, the sources of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global source line through second access transistors, the gates of the floating gate memory cells in each row of floating gate memory cells being connected to a respective word line;
• controllably providing a voltage of a first polarity between the gate and the drain of one or more selected cells in a sector to program the selected cell by Fowler Nordheim tunneling without disturbing the state of other cells;
• and,
• controllably providing a voltage of a second polarity opposite the first polarity between the gate and the drain of one or more selected rows of cells to erase the selected rows of cells by Fowler Nordheim tunneling without disturbing cells in unselected rows of cells.

A low power program and erase flash memory method comprising:

• providing an array of rows and columns of floating gate memory cells, each memory cell having a source, a drain, a gate and a floating gate, the array including a global bit line and a global source line for each column of cells, the rows of cells being grouped in sectors, each sector including a predetermined number of rows, the drains of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global bit line through first access transistors, the sources of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global source line through second access transistors, the gates of the floating gate memory cells in each row of floating gate memory cells being connected to a respective word line;
• controllably providing a voltage of a first polarity between the gate and the drain of one or more selected cells in a sector to program the selected cell by Fowler Nordheim tunneling and restricting voltages on floating gate memory cells not intended to be programmed to lesser voltages not disturbing the state of the floating gate memory cells not intended to be programmed;
• and,
• controllably providing a voltage of a second polarity opposite the first polarity between the gate and the drain of one or more selected rows of cells to erase the selected rows of cells by Fowler Nordheim tunneling and restricting voltages on floating gate memory cells not intended to be erased to lesser voltages not disturbing the programming of the floating gate memory cells not intended to be erased.