Erasure pointer error correction

A memory device comprising:

• a memory array containing a plurality of memory cells arranged into a plurality of segments, each segment containing ECC codes;
• a data buffer;
• a host transfer circuit coupled to the data buffer;
• and
• one or more ECC generator/checker circuits, where the data buffer and the one or more ECC generator/checker circuits are coupled to receive a selected read data segment;
• wherein N is a maximum number of bad bits recorded for each segment of the memory array;
• and
• wherein the memory device is adapted to correct the selected read data segment as it is read from the memory array utilizing the one or more ECC generator/checker circuits such that the one or more ECC generator/checker circuits evaluate the selected read data segment with differing states of the N bad bits and where the memory device selects the state of the N bad bits and selected read data segent that correctly evaluated in an ECC generator/checker to transfer through the host transfer circuit.

A Flash memory system, comprising:

• at least one Flash memory device, wherein the at least one Flash memory device contains a memory array with a plurality of floating gate memory cells arranged into a plurality of sectors in a plurality of erase blocks, wherein each erase block of the plurality of erase blocks contains a plurality of physical row pages, each physical row page containing one or more paired data sectors and ECC codes;
• and
• a Flash memory control circuit coupled to the at least one Flash memory device, wherein the Flash memory control circuit comprises,
• a data buffer,
• a host transfer circuit coupled to the data buffer, and
• two ECC generator/checker circuits, where the data buffer and the two ECC generator/checker circuits are coupled to receive a selected read data sector and ECC code;
• wherein a record of one known bad/questionable bit, if any, is recorded for each sector of each Flash memory device;
• and
• wherein the Flash memory control circuit is adapted to correct the selected read data sector utilizing the ECC code and the two ECC generator/checker circuits such that the two ECC generator/checker circuits evaluate the selected read data sector in parallel with differing states of the known bad bit and where the Flash memory control circuit selects the state of the known bad bit and selected read data sector to transfer through the host transfer circuit that evaluated correctly in an ECC generator/checker.

A memory controller comprising:

• a host interface;
• a memory device interface for one or more memory devices, wherein each of the one or more memory devices has a plurality of segments, and wherein each segment of the plurality of segments contains an ECC code;
• a data buffer coupled to the memory device interface;
• a host transfer circuit coupled to the data buffer and to the host interface;
• and
• one or more ECC generator/checker circuits, where the data buffer and the one or more ECC generator/checker circuits are coupled to receive a selected read data segment;
• wherein N is a maximum number of bad bits recorded for each segment of the at least one memory device;
• and
• wherein the memory controller is adapted to correct the selected read data segment as it is read from the one or more memory devices utilizing the one or more ECC generator/checker circuits such that each ECC generator circuit evaluates the selected read data segment where the N bad bits are in a differing selected state in each ECC generator/checker and where the memory controller selects the state of the N bad bits with the selected read data segment that matches the selected state of the N bad bits utilized in a correctly evaluating ECC generator/checker that evaluates a correct read data segment.

A system comprising:

• a host coupled to a memory system, wherein the memory system comprises:
• at least one memory device, wherein the at least one memory device contains a memory array with a plurality of memory cells arranged in one or more data segments, where each data segment contains an ECC code;
• and
• a memory control circuit coupled to the at least one memory device, wherein the memory control circuit comprises,
• a data buffer,
• a host transfer circuit coupled to the data buffer, and
• one or more ECC generator/checker circuits, where the data buffer and the one or more ECC generator/checker circuits are coupled to receive a selected read data segment;
• wherein N is a maximum number of bad bits recorded for each segment of the at least one memory device;
• and
• wherein the memory control circuit is adapted to correct the selected read data segment as it is read from the at least one memory device utilizing the one or more ECC generator/checker circuits such that the one or more ECC generator/checker circuits evaluate the selected read data segment with differing states of the N bad bits and where the memory control circuit selects the state of the N bad bits and selected read data segment that correctly evaluated in an ECC generator/checker to transfer through the host transfer circuit.

A method of operating a memory system comprising:

• reading a data segment of a plurality of segments from a selected memory device of one or more memory devices, where the location of one to N bad/questionable bits of each data segment are recorded, and wherein each segment of the plurality of segments contains an ECC code;
• error checking the read data segment by evaluating the read data segment in one or more ECC checks for each possible state of the one to N bad/questionable bits;
• selecting a correct state of the N bad/questionable bits from a correctly evaluating ECC check;
• and
• correcting the read data segment to correspond to the correct state of the N bad/questionable bits.

A method of operating a memory device comprising:

• reading a data segment of a plurality of segments from a memory array, where a location of one to N bad/questionable bits of each data segment are recorded and where each data segment has an ECC code;
• error checking the read data segment by evaluating the read data segment and ECC code in two or more parallel ECC checks, where each of the two or more parallel ECC checks evaluates the read data segment with the N bad/questionable bits in a differing state;
• selecting a correct state of the N bad/questionable bits from a correctly evaluating ECC check;
• and
• correcting the read data segment to correspond to the correct state of the N bad/questionable bits.

A method of operating a memory controller comprising:

• receiving a data segment of a plurality of segments from a selected memory device of one or more memory devices, where the location of one to N bad/questionable bits of each data segment are recorded, and wherein each segment of the plurality of segments contains an ECC code;
• error checking the read data segment by evaluating the read data segment in one or more ECC checks for each possible state of the one to N bad/questionable bits;
• selecting a correct state of the N bad/questionable bits from a correctly evaluating ECC check;
• and
• correcting the read data segment to correspond to the correct state of the N bad/questionable bits.

A method of correcting errors in a read data segment comprising:

• reading a data segment, where the location of one to N bad/questionable bits of the data segment are recorded, and wherein the read data segment contains an ECC code;
• error checking the read data segment by evaluating the read data segment in one or more ECC checks for each possible state of the one to N bad/questionable bits;
• selecting a correct state of the N bad/questionable bits from a correctly evaluating ECC check;
• and
• correcting the read data segment to correspond to the correct state of the N bad/questionable bits.

A memory system, comprising:

• at least one memory device, wherein the at least one memory device contains a memory array with a plurality of memory cells arranged in one or more data segments, where each data segment contains an ECC code;
• a memory control circuit coupled to the at least one memory device, wherein the memory control circuit comprises,
• a data buffer,
• a host transfer circuit coupled to the data buffer, and
• a ECC generator/checker circuit, where the data buffer and the ECC generator/checker circuit are coupled to receive a selected read data segment, and where N is a maximum number of bad bits recorded for each segment of the at least one memory device;
• and
• wherein the memory control circuit is adapted to error check and correct the selected read data segment as it is read from the at least one memory device by iteratively evaluating the read data segment and the ECC code in the ECC generator/checker, where each iteration evaluates the read data segment with the N bad bits in a differing state and correcting the read data segment to correspond to match the state of the N bad bits in a correctly evaluating iteration.

A memory controller comprising:

• a host interface;
• a memory device interface for one or more memory devices, wherein each of the one or more memory devices has a plurality of segments, and wherein each segment of the plurality of segments contains an ECC code;
• a data buffer coupled to the memory device interface;
• a host transfer circuit coupled to the data buffer and to the host interface;
• a ECC generator/checker circuit, where the data buffer and the ECC generator/checker circuit are coupled to receive a selected read data segment, and where N is a maximum number of bad bits recorded for each segment of the at least one memory device;
• and
• wherein the memory controller is adapted to error check and correct the selected read data segment as it is read from the at least one memory device by iteratively evaluating the read data segment and the ECC code in the ECC generator/checker, where each iteration evaluates the read data segment with the N bad bits in a differing state and correcting the read data segment to correspond to match the state of the N bad bits in a correctly evaluating iteration.

A memory controller, comprising:

• a data buffer,
• a host transfer circuit coupled to the data buffer
• a processor;
• an ECC generator/checker circuit, where the data buffer and the ECC generator/checker circuit are coupled to receive a read data segment from at least one memory device, where the read data segment contains an ECC code;
• wherein N is a maximum number of bad bit locations and likely states recorded for the read data segment of the at least one memory device;
• and
• wherein the memory controller is adapted to execute an error correction algorithm to correct a read data segment that the ECC generator/checker has evaluated as corrupt and where the error correction algorithm is configured to evaluate correction solutions based on the likely state of the N bad bits.

A memory controller comprising:

• a host interface;
• a memory device interface for one or more memory devices, wherein each of the one or more memory devices has a plurality of segments, and wherein each segment of the plurality of segments contains an ECC code;
• a data buffer coupled to the memory device interface;
• a host transfer circuit coupled to the data buffer and to the host interface;
• a ECC generator/checker circuit, where the data buffer and the ECC generator/checker circuit are coupled to receive a selected read data segment, and where N is a maximum number of bad bit locations recorded for each segment of the at least one memory device;
• and
• wherein the memory controller is adapted to execute an error correction algorithm to correct a read data segment that the ECC generator/checker has evaluated as corrupt and where the error correction algorithm is configured to evaluate correction solutions utilizing the locations of the recorded bad bits of the selected read data segment.

A method of correcting errors in a read data segment comprising:

• reading a data segment, where the location of one to N bad/questionable bits of the data segment are recorded, and wherein the segment contains an ECC code;
• error checking the read data segment by evaluating the read data segment with an ECC block code check;
• and
• error correcting the read data segment with an ECC block code error correction algorithm if the read data segment error checks as corrupt utilizing the locations one to N recorded bad/questionable bits as input to extend a maximum number of corrupt bits that are correctable by the ECC block code error correction algorithm utilizing the ECC code of the read data segment.

A method of correcting errors in a read data segment comprising:

• reading a data segment, where the location and likely state of one to N bad/questionable bits of the data segment are recorded, and wherein the segment contains an ECC code;
• error checking the read data segment by evaluating the read data segment with an ECC block code check;
• and
• error correcting the read data segment with an ECC block code error correction algorithm if the read data segment error checks as corrupt utilizing the locations and state of the one to N recorded bad/questionable bits as input to generate a correction and where the error correction algorithm is configured to evaluate correction solutions based on the likely state of the N bad bits.