System and method for reducing patterning variability in integrated circuit manufacturing through mask layout corrections

A method of compensating a target layout design for use in manufacture of integrated circuit devices, said method comprising:

• deriving a systematic variability signature, on a full reticle field-wide basis, based on process and equipment conditions applicable to the manufacturing process,
• generating compensation models or rules from the systematic variability signature, wherein the effects of said models or rules encompass the whole reticle field and are field location dependent, and
• applying the compensation models or rules to the target layout design, in a field location dependent manner, to produce a compensated layout design,
• and wherein the target layout design describes the physical layout of a fabrication layer of mutually adjacent instances of multiple integrated circuit designs within a reticle field, the step of deriving the variability signature comprises dividing the reticle field into multiple compensation zones, whereby each compensation zone contains features of the target layout design, and the step of generating compensation models or rules from the variability signature comprises generating compensation models or rules for the compensation zones respectively.

A method of compensating a target layout design for use in manufacture of integrated circuit devices, said method comprising:

• receiving the target layout design from a customer,
• deriving a systematic variability signature, on a full reticle field-wide basis, based on process and equipment conditions applicable to the manufacturing process,
• generating compensation models or rules from the systematic variability signature, wherein the effects of said models or rules encompass the whole reticle field and are field location dependent, and
• applying the compensation models or rules to the target layout design, in a field location dependent manner, to produce a compensated layout design,
• and wherein the process and equipment conditions are specific to a photolithographic patterning tool used by a wafer fabrication facility in a wafer exposure stage of the manufacturing process, and the method further comprises delivering the compensated layout design to a mask manufacturer for manufacture of a mask including a reticle in accordance with the compensated layout design, and delivering the mask to the wafer fabrication facility for patterning a layer of a wafer with the mask using the specific photolithographic patterning tool.

A method of compensating one or more target layout designs used in manufacture of integrated circuit devices, wherein:

• one or more customers specify one mask making and wafer fabrication process flow to a support service provider and each customer delivers one or more target layout designs intended for the specified mask making and wafer fabrication process flow to the support service provider,
• for the mask making and wafer fabrication process flow specified by the customers, the support service provider performs a characterization step to derive a systematic variability signature based on process and equipment conditions specific to the mask making and wafer fabrication process flow and generates compensation models or rules from the variability signature,
• for each target layout design, the support service provider applies the compensation models or rules generated from the variability signature based on the process and equipment conditions specific to the mask making and wafer fabrication process flow specified by the customer to generate a compensated layout design, and
• the support service provider delivers each compensated layout design to the customer, to a mask manufacturer, or directly to a device manufacturing facility.