Back to results
US 7,318,017 B2Granted
Collecting and exporting on-chip data processor trace and timing information with differing collection and export formats
AssigneeTexas Instruments Incorporated
InventorGary L. Swoboda
Life of this patent
Estimating the term…
Abstract
Data processor emulation information that has been collected and arranged into a plurality of first information blocks during the collection process is re-arranged into a plurality of second information blocks which differ in size from the first information blocks. A sequence of the second information blocks is output from the data processor via a plurality of terminals thereof.
Claims34
A method of exporting emulation information from a data processor integrated circuit, comprising:
- collecting internal emulation information from a data processor;
- arranging the collected emulation information into a plurality of first information blocks organized in a sequence, each of said first information blocks having a first fixed size, wherein each of a plurality of consecutive ones of said first information blocks contains a constituent bit of a multi-bit signal used by the data processor;
- receiving the plurality of first information blocks and arranging the emulation information contained therein into a plurality of second information blocks organized in a sequence, each of said second information blocks having a second fixed size which differs from the first fixed size of the first information blocks, wherein each of a plurality of consecutive ones of said second information blocks contains a constituent bit of said multi-bit signal;
- and
- driving from the data processor integrated circuit to a host external to the data processor integrated circuit electrical signals that correspond to said sequence of second information blocks.
2 more elements
An integrated circuit, comprising:
- a data processor for performing data processing operations;
- a collector coupled to said data processor for collecting emulation information from said data processor and arranging said emulation information into a plurality of first information blocks organized in a sequence, each of said first information blocks having a first fixed size, wherein each of a plurality of consecutive ones of said first information blocks contains a constituent bit of a multi-bit signal used by said data processor;
- an exporter coupled to said collector for receiving therefrom said plurality of first information blocks and arranging said emulation information contained therein into a plurality of second information blocks organized in a sequence, each of said second information blocks having a second fixed size which differs from the first fixed size of said first information blocks, wherein each of a plurality of consecutive ones of said second information blocks contains a constituent bit of said multi-bit signal;
- a plurality of terminals for outputting information;
- and
- said exporter coupled to said terminals for outputting said sequence of second information blocks via said terminals.
3 more elements
A data processing system, comprising:
- an integrated circuit, including a data processor for performing data processing operations;
- an emulation controller coupled to said integrated circuit for controlling emulation operations of said data processor;
- said integrated circuit including an apparatus coupled between said data processor and said emulation controller for providing emulation information about said data processing operations, said apparatus including a collector coupled to said data processor for collecting said emulation information from said data processor and arranging said emulation information into a plurality of first information blocks organized in a sequence, each of said first information blocks having a first fixed size, wherein each of a plurality of consecutive ones of said first information blocks contains a constituent bit of a multi-bit signal used by said data processor, and an exporter coupled to said collector for receiving said plurality of first information blocks and arranging said emulation information contained therein into a plurality of second information blocks organized in a sequence, each of said second information blocks having a second fixed size which differs from the first fixed size of said first information blocks, wherein each of a plurality of consecutive ones of said second information blocks contains a constituent bit of said multi-bit signal;
- and
- said integrated circuit including a plurality of terminals coupled to said emulation controller for outputting information to said emulation controller, said exporter coupled to said terminals for outputting said sequence of second information blocks to said emulation controller via said terminals.
2 more elements
Dependencies are inferred from the claim text.