Clock distribution network using feedback for skew compensation and jitter filtering
AssigneeIntel Corporation
InventorMartin Saint-Laurent
Life of this patent
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Abstract
A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the IC at respective local clock regions. A master clock generator generates a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions.
Claims11
An architecture for clock distribution on an integrated circuit (IC), comprising:
- a clock distribution network;
- a plurality of clock processor nodes distributed throughout the clock distribution network on the IC at respective local clock regions;
- a master clock generator to generate a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions;
- and
- wherein:
- the master clock generator corresponds to a master delay locked loop (DLL) to generate and keep the master clock synchronized responsive to a system clock;
- and
- each clock processor node at each local clock region comprises:
- a slave phase-locked loop (PLL) to generate a high-frequency core clock for its local region and to attenuate the clock jitter from the master clock introduced by the clock distribution network;
- and
- a variable-delay element (VDE) to compensate the clock skew from the master clock introduced by the clock distribution network.
A system, comprising:
- a master clock generator to generate a master clock for distribution;
- an external crystal oscillator coupled to the master clock generator to generate a system clock used by the master clock generator;
- and
- a plurality of clock processor nodes, each clock processor node including:
- a slave phase-locked loop (PLL) to attenuate clock jitter from the master clock introduced by a clock distribution network;
- a variable-delay element (VDE) to compensate clock skew from the master clock introduced by the clock distribution network;
- and
- an alignment control unit to control delay variations of the variable-delay element (VDE) so as to align the master clock for clock skew compensation.
Dependencies are inferred from the claim text.