Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays

A method of operating a memory array comprising a plurality of memory cells disposed on a semiconductor substrate, wherein each of said memory cells comprises:

• a source region and a drain region disposed below a surface of the substrate and separated by a channel region;
• a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height;
• a charge storage layer disposed above the tunnel dielectric structure;
• an insulating layer disposed above the charge storage layer;
• and a gate electrode disposed above the insulating layer;
• the method comprising:
• applying self-converging reset/erase voltages to the substrate and the gate electrode in each memory cell to be reset/erased;
• programming at least one of the plurality of memory cells;
• and
• reading at least one of the plurality of memory cells by applying a voltage between an erased state level and a programmed state level of at least one of the memory devices.