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US 7,312,637 B2Granted
Enhanced timing margin memory interface
AssigneeThunder Creative Technologies, Inc.
InventorsRobert D. Washburn, Robert F. McClanahan
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Abstract
The present invention is an electronic circuit that significantly enhances timing margin in high-speed, digital memory modules. The circuit is implemented is applicable to all switching waveforms on both control and data signal lines that drive the memory bus. Implementation of the present invention also provides a significant reduction in power dissipation compared to memory modules of comparable size and speed utilizing the present art.
Claims23
A memory interface comprising:
- a first memory interface logic input signal coupled through a first transition time adjust circuit and having a first time adjusted output coupled directly to a first input of an OR gate;
- a second memory interface logic input signal coupled through a second transition time adjust circuit and having a second time adjusted output coupled directly to a second input of an OR gate;
- such that only the first and second time adjusted outputs are selectable at said OR gate.
A memory interface comprising:
- a first input signal coupled to a first input of an OR gate through a first transition time adjust circuit;
- a second input signal coupled to a second input of an OR gate through a second transition time adjust circuit;
- wherein the first transition time adjust circuit comprises:
- a first and second signal path for receiving the first input signal;
- the first signal path comprising a first transistor having an output coupled through first and second resistors to an output node;
- the second signal path comprising a second transistor coupled through third and fourth resistors to the output node.
3 more elements
Dependencies are inferred from the claim text.