Phase locked loop circuit having deadlock protection circuit and methods of operating same

A phase-locked loop (PLL) integrated circuit, comprising:

• a phase-frequency detector responsive to an input clock signal and a divided clock signal;
• a voltage-controlled oscillator configured to generate at least a first output clock signal in response to a control signal;
• and
• a divide-by-N feedback circuit configured to generate the divided clock signal in response to the first output clock signal, said divide-by-N feedback circuit comprising:
• a sub-divider having an input electrically coupled to an output of said voltage-controlled oscillator, said sub-divider configured to divide a frequency of the first output clock signal by N1, where N1 is a first integer greater than one;
• a selector having a first input electrically coupled to the output of said voltage-controlled oscillator and a second input electrically coupled to an output of the sub-divider, said selector responsive to a selection signal that controls which of the first and second inputs of said selector is electrically connected to an output of said selector;
• a main divider having an input electrically coupled to the output of said selector, said main divider configured to generate the divided clock signal by dividing a frequency of a clock signal generated at the output of selector by N2, where N2 is a second integer greater than one;
• and
• a comparator configured to generate the selection signal at an output thereof, said comparator having a first input electrically coupled to the output of said voltage-controlled oscillator and a second input responsive to a reference voltage.