US 7,307,003 B2 · Method of forming a multi-layer semiconductor structure incorporating a processing handle member

Abstract

A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of a first conductive member defined on the first structure. A conductive material is disposed in the first via-hole such that a first end of the conductive material is in electrical communication with the first conductive member and a second end of the conductive material is exposed at the bottom surface of the first structure. A second interface is disposed over at least the second end of the conductive material, which serves as a bonding and/or electrical interface between the first conductive member defined on the first structure and a second structure of the multi-layer semiconductor device structure.

Claims45

Dependent claims

A method of providing a multi-layer semiconductor structure, the method comprising:

providing a first semiconductor structure having first and second opposing surfaces;
and
disposing a laminate layer over a first one of the first and second opposing surfaces of the first semiconductor structure to provide a first semiconductor structure having a laminate layer disposed thereon wherein disposing a laminate layer comprises providing a layer corresponding to a release layer and providing a layer corresponding to a fusion layer;
disposing a handle member over the laminate layer.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

10/749,103Filed 30 Dec 2003 · us provisional application

Priority

31 Dec 2002

Published

US 2004/0219765 A14 Nov 2004

Granted

11 Dec 2007

Term ends

Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10P 72/74
For supporting or gripping: using temporarily an auxiliary support
H10W 20/0234
The interconnections being through-semiconductor vias: comprising etching via holes that stop on pads or on electrodes
H10W 20/0242
The interconnections being through-semiconductor vias: comprising etching via holes from the back sides of the chips, wafers or substrates
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Method of forming a multi-layer semiconductor structure incorporating a processing handle member

Life of this patent

Method of forming a multi-layer semiconductor structure incorporating a processing handle member

Life of this patent

Abstract

Claims45