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US 7,304,355 B2Granted
Three-dimensional-memory-based self-test integrated circuits and methods
OwnerGuobiao Zhanginventor
Life of this patent
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Abstract
The three-dimensional memory (3D-M) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, 3D-M has minimum impact to the layout of the CUT. The CUT with integrated 3D-M supports IC self-test. Moreover, with a large bandwidth with the CUT, 3DM-based IC self-test enables at-speed test.
Claims12
An integrated circuit (IC) supporting non-electrically-programmable three-dimensional memory (NEP-3DM)-based self-test (NEP-3DMST), comprising
- a substrate circuit, said substrate circuit further comprising a circuit-under-test (CUT) and a peripheral circuit;
- and,
- at least an NEP-3DM level stacked on said substrate circuit, at least a portion of said NEP-3DM level storing at least a portion of test data and/or test-data seeds for said CUT and being connected with said peripheral circuit through a plurality of inter-level connecting vias.
Dependencies are inferred from the claim text.