US 7,301,541 B2Granted

Programmable processor and method with wide operations

AssigneeMicroUnity Systems Engineering, Inc.

InventorsCraig Hansen, John Moussouris, Alexia Massalin

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Abstract

A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Claims15

Dependent claims

A programmable processor comprising:

a first memory system having a first data path width;
a second memory system and a third memory system, wherein each of the second memory system and the third memory system have a data path width which is greater than the first data path width;
a first copying module configured to copy a first memory operand portion from the first memory system to the second memory system, the first memory operand portion having the first data path width, and configured to copy a second memory operand portion from the first memory system to the second memory system, the second memory operand portion having the first data path width and being catenated in the second memory system with the first memory operand portion, thereby forming first catenated data;
a second copying module configured to copy a third memory operand portion from the first memory system to the third memory system, the third memory operand portion having the
first data path width, and configured to copy a fourth memory operand portion from the first memory system to the third memory system, the fourth memory operand portion having the first data path width and being catenated in the third memory system with the third memory operand portion, thereby forming second catenated data;
and
a functional unit configured to perform computations using the first catenated data and the second catenated data.

4 more elements

A programmable processor comprising:

a firstmemory system having a first data path width,
a second memory system and a third memory system each of the second memory system and the third memory system having a data path width which is greater than the first data path width;
a first copying module configured to copy a first memory operand portion from the first memory system to the second memory system, the first memory operand portion having the first data path width, and configured to copy a second memory operand portion from the first memory system to the second memory system, the second memory operand portion having the first data path width and being catenated in the second memory system with the first memory operand portion, thereby forming first catenated data;
a second copying module configured to copy a third memory operand portion from the third memory system to the first memory system, the
third memory operand portion having the first data path width and containing a portion of a second catenated data, and copy a fourth memory operand portion from the third memory system to the first memory system, the fourth memory operand portion having the first data path width and containing a portion of the second catenated data, wherein the fourth memory operand portion is catenated in the third memory system with the third memory operand portion;
and
a functional unit configured to perform computations using the first catenated data to produce the second catenated data.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/616,303Filed 10 Jul 2003 · continuation
Priority: 16 Aug 1995
Published: US 2004/0098548 A120 May 2004
Granted: 27 Nov 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification43 codes

G06F 9/3001
To perform operations on data operands: arithmetic instructions
G06F 9/30
Using stored programs, i.e. using an internal store of processing equipment to receive or retain programs: arrangements for executing machine…
G06F 9/30007
Arrangements for executing specific machine instructions: to perform operations on data operands
G06F 9/30014
Arithmetic instructions: with variable precision

Family

Application08/516,036Parent of this division · filed 16 Aug 1995
Application08/754,827Parent of this continuation · filed 22 Nov 1996
Application60/097,635Us provisional application · filed 24 Aug 1998
Application09/169,963Parent of this continuation-in-part · filed 13 Oct 1998
Application09/382,402Parent of this continuation · filed 24 Aug 1999
Application09/922,319Parent of this continuation · filed 2 Aug 2001
Application60/394,665Us provisional application · filed 10 Jul 2002
US 2004/0098548 A1Pre-grant publication · published 20 May 2004
US 6,725,356 B2Parent of this continuation
US 6,295,599 B1Parent of this continuation
US 6,006,318 AParent of this continuation-in-part
Application09/382,402Parent of this continuation-in-part
US 5,822,603 AParent of this continuation
Application09/169,963Parent of this continuation
US 5,742,840 AParent of this division
Application08/754,827Parent of this division
US 2002/0133682 A1Published application
US 7,301,541 B2This patent

From the US filing history. Foreign family members aren’t listed.