System and method for converting control flow graph representations to control-dataflow graph representations

A method of forming a control-dataflow graph comprising:

• separating hardware logic module calls in a basic block of a control-flow graph into individual code blocks;
• combining two or more of the individual code blocks into a combined code block;
• and
• converting the combined code block into at least a portion of the control-dataflow graph and wherein nodes in the control-dataflow graph represent functional units and directed edges between the nodes represent data connections that bring output data items from one functional unit to the inputs of other functional units
• portioning the control-dataflow graph into a reconfigurable hardware portion and an instruction processor portion, wherein the reconfigurable hardware portion is converted into a bit-stream data file that can be loaded into individual circuits in a reconfigurable processor and wherein the instruction processor portion is converted into an instruction processor object file;
• and
• linking together the bit-stream data file and the instruction processor object file to form a unified executable capable of configuring the reconfigurable processor to run a high level language.

A computer program product comprising:

• a computer usabie medium having a computer readabie program code embodied therein for causing a formation of a control-dataflow graph for converting high level languages into executable code, the computer readable program code comprising:
• computer readable program code for causing a computer to separate hardware logic module calls in a basic block of a control flow graph into individual code blocks;
• computer readable program code for causing the computer to combine two or more of the individual code blocks into a combined code block;
• computer readable program code for causing the computer to convert the combined code block into at least a portion of the control-dataflow graph and wherein nodes in the control-dataflow graph represent functional units and directed edges between the nodes represent data connections that bring output data items from one functional unit to the inputs of other functional units
• computer readable program code for portioning the control-dataflow graph into a reconfigurable hardware portion and an instruction processor portion, wherein the reconfigurable hardware portion is converted into a bit-stream data file that can be loaded into individual circuits in a reconfigurable processor and wherein the instruction processor portion is converted into an instruction processor object file;
• and
• computer readable program code for linking together the bit-stream data file and the instruction processor object file to form a unified executable capable of configuring the reconfigurable processor to run a high level language.