# US 7,295,624 B2 · Wireless system with hybrid automatic retransmission request in interference-limited communications

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- Number: US 7,295,624 B2
- Document ID: US7295624B2
- Status: Granted
- Kind: B2
- Application number: 10/260,761
- Filed: 2002-09-30
- Published: 2004-10-14
- Granted: 2007-11-13
- Earliest claimed: 2002-03-06
- Assignees: Texas Instruments Incorporated
- Inventors: Eko N. Onggosanusi; Anand G Dabak; Timothy M. Schmidl
- Web page: https://patentgrep.com/patent/US7295624B2

## CPC

- H04L 25/03038: {with a non-recursive structure (H04L25/03031 takes precedence)}
- H04L 1/06: using space diversity
- H04L 1/1812: Hybrid protocols; Hybrid automatic repeat request [HARQ]
- H04L 25/067: {providing soft decisions, i.e. decisions together with an estimate of reliability (H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178)}
- H04L 1/16: in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L 25/0228: {with direct estimation from sounding signals}
- H04L 2025/0342: {QAM}
- H04L 2025/03624: {Zero-forcing}
- Y10S 370/913: Wireless or radio
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A wireless receiver for receiving signals from an interference-limited transmitter in an interference-limited system comprising at least one transmit antenna, wherein the signals comprise a plurality of symbols. The receiver comprises a plurality of receive antennas and collection circuitry for collecting a plurality of signal samples with at least one symbol and interference effects. The receiver also comprises suppression circuitry, accumulation circuitry, circuitry for providing estimates of a group of bits, error detection circuitry and circuitry for requesting the transmitter to transmit a retransmission of a packet in response to detecting an error.

## Claims

### Claim 1

A wireless receiver for receiving signals from a transmitter comprising at least one transmit antenna in a wireless system, wherein the signals comprise a plurality of symbols and wherein each symbol in the plurality of symbols corresponds to a number of bits, the receiver comprising:
a plurality of receive antennas;
collection circuitry, coupled to the plurality of receive antennas, for collecting a plurality of signal samples from the plurality of receive antennas, wherein the plurality of signal samples comprise at least one symbol and interference effects and correspond to each packet in a number I+1 of packets transmitted by the transmitter, wherein each packet of the number I+1 of packets as transmitted by the transmitter comprise at least a portion of a same set of symbols and are re-transmitted by the transmitter in response to a request from the receiver;
suppression circuitry, coupled to the collection circuitry, for suppressing the interference effects in the number I+1 of packets;
circuitry for accumulating a result corresponding to each packet of the number I+1 of packets, wherein the result corresponds to an output of the collection circuitry, and for the accumulating either prior to or after the operation of said suppression circuitry;
circuitry responsive to signals from the suppression circuitry and for providing estimates of a group of bits;
detection circuitry for detecting an error in a packet that comprises the group of bits;
circuitry for sending the request to the transmitter to transmit a retransmission of a packet in response to the detection circuitry detecting the error; and
circuitry, coupled to the plurality of receive antennas, for determining a channel estimate matrix; and
wherein the circuitry for accumulating is coupled between the collection circuitry and the suppression circuitry; and
wherein the suppression circuitry is responsive to the accumulated results corresponding to each packet of the number I+1 of packets.

### Claim 2 (depends on 1)

The receiver of claim 1 and further comprising circuitry, coupled to the plurality of receive antennas, for determining a channel estimate matrix.

### Claim 3 (depends on 2)

The receiver of claim 2:
wherein the plurality of symbols comprises pilot symbols; and
wherein the circuitry for determining a channel estimate matrix determines the channel estimate matrix in response to the pilot symbols.

### Claim 4 (depends on 2)

The receiver of claim 2 and further comprising circuitry for increasing the signal to noise ratio of the received signals in response to the channel estimate matrix.

### Claim 5 (depends on 2)

The receiver of claim 2 and further comprising circuitry for increasing the signal to noise ratio of the received signals in response to a conjugate transpose of the channel estimate matrix.

### Claim 6 (depends on 2)

The receiver of claim 2:
and further comprising circuitry for determining a plurality of channel estimate matrices; and
wherein each channel estimate matrix in the plurality of channel estimate matrices corresponds to a respective packet in the number I+1 of packets transmitted by the transmitter.

### Claim 7 (depends on 6)

The receiver of claim 6 wherein the circuitry for determining a plurality of channel estimate matrices produces a result corresponding to each packet of the number I+1 of packets by multiplying the received signals corresponding to each packet of the number I+1 of packets times a respective conjugate transpose of the channel estimate matrix corresponding to each packet of the number I+1 of packets.

### Claim 8 (depends on 7)

The receiver of claim 7 and further comprising circuitry for determining a product corresponding to each packet of the number I+1 of packets by multiplying a conjugate transpose of the channel estimate matrix corresponding to each packet of the I+1 packets times a respective channel estimate matrix corresponding to each packet of the number I+1 of packets.

### Claim 9 (depends on 8)

The receiver of claim 8 and further comprising circuitry for accumulating the product corresponding to each packet of the number I+1 of packets.

### Claim 10 (depends on 9)

The receiver of claim 9 wherein the suppression circuitry is further responsive to the accumulated products.

### Claim 11 (depends on 9)

The receiver of claim 9 wherein the suppression circuitry is selected from a group consisting of zero forcing, minimum mean square error, iterative, and maximum likelihood detection.

### Claim 12 (depends on 9)

The receiver of claim 9:
wherein the suppression circuitry comprises maximum likelihood detection circuitry; and
further comprising circuitry for determining encoded bit probabilities from which the estimates of a group of bits are determined.

### Claim 13 (depends on 9)

The receiver of claim 9:
wherein the suppression circuitry provides a corresponding output signal responsive to the accumulated products and the accumulated results; and
wherein the circuitry for requesting is responsive to the output signal.

### Claim 14 (depends on 6)

The receiver of claim 6 wherein the suppression circuitry suppresses the interference effects in each individual one of each result corresponding to each packet of the number I+1 of packets.

### Claim 15 (depends on 14)

The receiver of claim 14:
and further comprising circuitry for determining a product corresponding to each packet of the number I+1 of packets by multiplying a conjugate transpose of the channel estimate matrix corresponding to each packet of the I+1 packets times a respective channel estimate matrix corresponding to each packet of the number I+1 of packets; and
wherein the suppression circuitry suppresses the interference effects in each individual one of each result corresponding to each packet of the number I+1 of packets in response to the product corresponding to each packet of the number I+1 of packets.

### Claim 16 (depends on 15)

The receiver of claim 15 wherein the suppression circuitry is selected from a group consisting of zero forcing, minimum mean square error, iterative, and maximum likelihood detection.

### Claim 17 (depends on 15)

The receiver of claim 15:
wherein the suppression circuitry comprises maximum likelihood detection circuitry; and
further comprising circuitry for determining encoded bit probabilities from which the estimates of a group of bits are determined.

### Claim 18 (depends on 1)

The receiver of claim 1 wherein the signals from the transmitter comprise a code division multiple access format.

### Claim 19 (depends on 1)

The receiver of claim 1 wherein the signals from the transmitter comprise a multiple-input multiple-output format.

### Claim 20 (depends on 1)

The receiver of claim 1 wherein the signals from the transmitter comprise a time division multiple access format.

### Claim 21 (depends on 1)

The receiver of claim 1 and further comprising circuitry for receiving signals from the suppression circuitry and for providing estimates of the symbols.

### Claim 22 (depends on 1)

The receiver of claim 1 in combination with the transmitter.

### Claim 23

A method of operating a wireless receiver to receive signals from a transmitter comprising at least one transmit antenna in a wireless system, wherein the signals comprise a plurality of symbols and wherein each symbol in the plurality of symbols corresponds to a number of bits, the method comprising:
collecting a plurality of signal samples from a plurality of receive antennas, wherein the plurality of signal samples comprise at least one symbol and interference effects and correspond to each packet in a number I+1 of packets transmitted by the transmitter, wherein each packet of the number I+1 of packets as transmitted by the transmitter comprise at least a portion of a same set of symbols and are re-transmitted by the transmitter in response to a request from the receiver;
suppressing the interference effects in the number I+1 of packets;
accumulating a result corresponding to each packet of the number I+1 of packets, wherein the result corresponds to an output from the collecting step, and wherein the accumulating step occurs either prior to or after the suppressing step with respect to the number I+1 of packets;
responsive to signals following the step of suppressing the interference effects, providing estimates of a group of bits;
detecting whether there is an error in a packet that comprises the group of bits; and
in response detecting the error, requesting the transmitter to transmit a retransmission of a packet; and
wherein the accumulating step is done between the collection and suppression steps; and
wherein the suppressing step is further responsive to the accumulated products.

### Claim 24 (depends on 23)

The method of claim 23 and further comprising determining a channel estimate matrix in response to signals received from at least one receive antenna.

### Claim 25 (depends on 24)

The method of claim 24 and further comprising increasing the signal to noise ratio of the received signals in response to a conjugate transpose of the channel estimate matrix.

### Claim 26 (depends on 24)

The method of claim 24:
and further comprising determining a plurality of channel estimate matrices; and
wherein each channel estimate matrix in the plurality of channel estimate matrices corresponds to a respective packet in the number I+1 of packets transmitted by the transmitter.

### Claim 27 (depends on 26)

The method of claim 26 wherein the determining step produces a result corresponding to each packet of the number I+1 of packets by multiplying the received signals corresponding to each packet of the number I+1 of packets times a respective conjugate transpose of the channel estimate matrix corresponding to each packet of the number I+1 of packets.

### Claim 28 (depends on 26)

The method of claim 26 and further comprising determining a product corresponding to each packet of the number I+1 of packets by multiplying a conjugate transpose of the channel estimate matrix corresponding to each packet of the I+1 packets times a respective channel estimate matrix corresponding to each packet of the number I+1 of packets.

### Claim 29 (depends on 28)

The method of claim 28 and further comprising accumulating the product corresponding to each packet of the number I+1 of packets.

### Claim 30 (depends on 26)

The method of claim 26 wherein the suppressing step suppresses the interference effects in each individual one of each result corresponding to each packet of the number I+1 of packets.

### Claim 31 (depends on 30)

The method of claim 30:
and further comprising determining a product corresponding to each packet of the number I+1 of packets by multiplying a conjugate transpose of the channel estimate matrix corresponding to each packet of the I+1 packets times a respective channel estimate matrix corresponding to each packet of the number I+1 of packets; and
wherein the suppressing step suppresses the interference effects in each individual one of each result corresponding to each packet of the number I+1 of packets in response to the product corresponding to each packet of the number I+1 of packets.

### Claim 32 (depends on 1)

The receiver of claim 1 wherein the circuitry for sending the request is further for sending to the transmitter an acknowledgement when a packet is successfully detected.