Limit-cycle-free FIR/IIR halfband digital filter with shared registers for high-speed sigma-delta A/D and D/A converters
AssigneeTexas Instruments Incorporated
InventorZhongnong Jiang
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Abstract
A multiplexed FIR/IIR digital filter structure (300) which offers linear phase response and low group delay by switching on a FIR filter portion (31) or a IIR filter portion (32). To reduce the silicon area, the FIR/IIR filter (300) shares registers which is enabled because the FIR and IIR processing do not use the registers at the same time but rather consecutively. Further, the multiplexed FIR/IIR digital filter structure (300) can offer limit-cycle-free IIR operation using two's-complement truncation in combination with positive valued allpass coefficients.
Claims16
A limit-cycle free digital filter comprising;
- a finite impulse response (FIR) filter having a first plurality of delay elements implemented for processing data;
- a infinite impulse response (IIR) filter having a second plurality of delay elements implemented for processing said data;
- wherein a shared plurality of delay elements is contained in said first plurality of delay elements and said shared plurality of delay elements is also contained in said second plurality of delay elements;
- a multiplexer system coupled to said FIR filter and said IIR filter for switching said shared plurality of delay elements therebetween;
- and
- wherein said shared plurality of delay elements are used consecutively for FIR filter data processing and IIR filter data processing.
A limit-cycle free digital filtering system comprising:
- a signal source for generating a digital signal;
- a digital filter having an Nth-order and coupled to said signal source for receiving and filtering said digital signal by performing a sequence of operations including delaying products of said digital signal with filter coefficients for each order of said digital filter, said digital filter comprising:
- a finite impulse response (FIR) filter having an input for receiving said digital signal and an output for outputting a filtered signal corresponding to said digital signal, said FIR filter further having an NFIRth-order and a plurality of delay elements corresponding to NFIR;
- a infinite impulse response (IIR) filter having an input for receiving said digital signals and an output for outputting a filtered signal corresponding to said digital signal, said IIR filter further having an NIIRth-order and a plurality of delay elements corresponding to NIIR;
- a multiplexer system coupled to said FIR filter and said IIR filter for switching a shared plurality of delay elements which are included in both said FIR filter and said IIR filter.
Dependencies are inferred from the claim text.