US 7,291,878 B2Granted

Ultra low-cost solid-state memory

AssigneeHitachi Global Storage Technologies Netherlands B.V.

InventorBarry Cushing Stipe

Life of this patent

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Abstract

A three-dimensional solid-state memory is formed from a plurality of bit lines, a plurality of layers, a plurality of tree structures and a plurality of plate lines. Bit lines extend in a first direction in a first plane. Each layer includes an array of memory cells, such as ferroelectric or hysteretic-resistor memory cells. Each tree structure corresponds to a bit line, has a trunk portion and at least one branch portion. The trunk portion of each tree structure extends from a corresponding bit line, and each tree structure corresponds to a plurality of layers. Each branch portion corresponds to at least one layer and extends from the trunk portion of a tree structure. Plate lines correspond to at least one layer and overlap the branch portion of each tree structure in at least one row of tree structures at a plurality of intersection regions.

Claims29

Dependent claims

A memory device, comprising:

a plurality of bit lines formed on a substrate and arranged substantially in a first plane and extending substantially in a first direction;
a plurality of layers, each layer having an array of memory cells;
a plurality of tree structures, at least one tree structure corresponding to each bit line, each tree structure having a trunk portion and at least one branch portion, each branch portion of a tree structure corresponding to at least one layer, the trunk portion of each tree structure extending from the substrate, each branch portion of a tree structure extending from the trunk portion of the tree structure, and each tree structure corresponding to a plurality of layers;
and
a plurality of plate line groups, each plate line group including a plurality of plate lines and corresponding to at least one layer, each respective plate line group overlapping branch portions of each tree structure in at least one row of tree structures at a plurality of intersection regions, a memory cell being located at each intersection region in a layer.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/751,740Filed 5 Jan 2004 · continuation in part
Priority: 3 Jun 2003
Published: US 2004/0245547 A19 Dec 2004
Granted: 6 Nov 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10B 53/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the memory core region
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 11/22
Using electric elements: using ferroelectric elements
G11C 11/5678
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using…