Active filter and method for scheduling transistor bridge trigger times for each phase of power grid

An active filter for compensation of variations in an apparatus current consumption from a three-phase power grid as a result of variations in the electrical loads of the apparatus, the active filter comprising:

• a transistor bridge arranged for reversal of the current direction connected between each of the three phases of the power grid and a DC-link;
• and
• a control system which comprises:
• (a) means for measuring load currents to the apparatus and identifying undesired frequency components,
• (b) means for controlling current direction, current magnitude and frequency content between the phases through the DC-link in such a manner that the frequency components are extinguished, and
• (c) means for operating with a repetitive real time process cycle configured to (1) determine a reference point in time, To, relative to the repetitive real time process cycle having a time period, (2) determine a control point in time for each transistor bridge for each one of the three phases of the power grid for triggering the corresponding transistor bridge, (3) convert the control point in time to an absolute control point in time by applying an absolute time correction thereto that is equal to the sum of the time period of the repetitive real time process cycle multiplied by the number of real time process cycles that have occurred since the reference point in time, To, and thereafter (4) trigger each transistor bridge using the corresponding absolute control point in time determined for the corresponding transistor bridge.

An active filter for compensation of variations in an apparatus current consumption from a power grid as a result of variations in the electrical loads of the apparatus, the active filter comprising:

• an electrical energy accumulator;
• a switching arrangement comprised of a pair of transistors for each phase of electrical power from the power grid with one of the transistors for each phase linked to the electrical energy accumulator and the other one of the transistors enabling current flow to be directed in one direction opposing current flow of the corresponding phase in the opposite direction when the one of the transistors is triggered and the other one of the transistors for each phase linked to the electrical energy accumulator and the one of the transistors enabling current flow to be directed in the opposite direction opposing current flow of the corresponding phase in the one direction when the other one of the transistors is triggered;
• a control device comprised of a processor configured to set a reference point in time, To, relative to a repetitive real time process cycle having a determinate time period, to determine a scheduled transistor trigger time for each phase, to convert the scheduled transistor trigger time to an absolute scheduled transistor trigger time by applying an absolute time correction to the scheduled transistor trigger time with the absolute time correction being equal to the determinate time period of the repetitive real time process cycle multiplied by the number of real time process cycles that have occurred from the reference point in time up until the present real time process cycle during which the scheduled transistor trigger time is set to occur, and triggering a designated one of the plurality of transistors when the absolute scheduled transistor trigger time arrives compensating for variation in the apparatus current consumption for the corresponding phase from the power grid.

An active filter for compensation of variations in an apparatus current consumption from a power grid as a result of variations in the electrical loads of the apparatus, the active filter comprising:

• a DC link;
• a transistor bridge comprised of a pair of transistors for each phase of electrical power from the power grid that are linked to each other and that are linked to the DC link;
• a plurality of inductors in series connecting each phase of the active filter to a corresponding phase of the power grid with a capacitor for each phase having one end connected to the corresponding phase between the plurality of series connected inductors for that phase and the capacitors for all of the phases having their opposite end connected to each other;
• and
• a control device comprised of a processor configured to carry out a repetitive real time process cycle having a determinate time period where (a) a reference point in time, To, marking the beginning of the real time process cycle is determined, (b) a scheduled transistor trigger time is determined for each transistor bridge of each phase, (c) an absolute scheduled transistor trigger time is determined for each transistor bridge of each phase by converting the corresponding scheduled transistor trigger time by adding an absolute time correction to the corresponding scheduled transistor trigger time that is equal to the determinate time period of the repetitive real time process cycle multiplied by the number of real time process cycles that have occurred from the reference point in time, To, until the current real time process cycle during which the scheduled transistor trigger time is set to occur, and thereafter (d) the transistors of each transistor bridge for each phase are triggered according to the corresponding absolute scheduled transistor trigger time compensating for variation in the apparatus current consumption for the corresponding phase.

A method for scheduling a process in a repetitive real time process cycle executed by an operating system in controlling an active filter comprising:

• (a) providing an active filter having a plurality of transistor bridges with a transistor bridge for each phase and a neutral of a power grid connected to a DC-link, a processor used in controlling switching of each transistor bridge, and an onboard clock;
• (b) setting a reference point in time, To, relative to the repetitive real time process cycle using the onboard clock with the repetitive real time process cycle having a time period;
• (c) scheduling a transistor bridge trigger time for each phase and the neutral;
• (d) converting the scheduled transistor bridge trigger time into an absolute scheduled transistor bridge trigger time for each corresponding transistor bridge by applying an absolute time correction to the scheduled transistor bridge trigger time with the absolute time correction being equal to the time period of the repetitive real time process cycle multiplied by the number of real time process cycles that have occurred from the reference point in time, To, up until the current real time process cycle during which the scheduled transistor bridge trigger time is set to occur;
• and
• (e) triggering each one of the transistor bridges when the absolute scheduled transistor bridge trigger time arrives for the corresponding transistor bridge.