# US 7,289,783 B2 · Mixer circuits and methods with matched bias currents

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- Number: US 7,289,783 B2
- Document ID: US7289783B2
- Status: Granted
- Kind: B2
- Application number: 11/262,685
- Filed: 2005-10-31
- Published: 2006-10-19
- Granted: 2007-10-30
- Earliest claimed: 2005-04-15
- Assignees: WiLinx, Inc.
- Inventors: Edris Rostami; Rahim Bagheri; Masoud Djafari; Abbas Komijani
- Web page: https://patentgrep.com/patent/US7289783B2

## CPC

- H03D 7/1458: {Double balanced arrangements, i.e. where both input signals are differential}
- H03D 7/1433: {using bipolar transistors (H03D7/145 takes precedence)}
- H03D 7/1441: {using field-effect transistors (H03D7/145 takes precedence)}
- H03D 7/1483: {comprising components for selecting a particular frequency component of the output}
- H03D 7/165: {at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature (combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002)}
- H03D 2200/0043: Bias and operating point
- H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66)

## Abstract

Embodiments of the present invention include circuits and methods for improving the spectral purity of mixer circuits. In one embodiment the present invention includes a mixer circuit including a bias circuit, the bias circuit comprising a first transistor having a gate, a source, and a drain, wherein the drain is coupled to a first input of the mixer circuit, a first sensing circuit coupled to the source of the first transistor, and a first comparison circuit coupled to the first sensing circuit, wherein the first comparison circuit receives a feedback signal from the first sensing circuit and a reference voltage, and in accordance therewith, generates a bias control signal to control the bias at the gate of the first transistor.

## Claims

### Claim 1

A mixer circuit comprising:
a first differential transistor having a gate, a source, and a drain, wherein the source of the first differential transistor is a first input of the mixer circuit;
a second differential transistor having a gate, a source, and a drain, wherein the source of the second differential transistor is a second input of the mixer circuit; and
a first capacitor coupled between the source of the first differential transistor and the source of the second differential transistor;
a first bias transistor having a gate, a source, and a drain, wherein the drain is coupled to the source of the first differential transistor;
a second bias transistor having a gate, a source, and a drain, wherein the drain is coupled to the source of the second differential transistor;
a first sensing circuit coupled to the source of the first bias transistor;
a second sensing circuit coupled to the source of the second bias transistor;
a first comparison circuit coupled to the first sensing circuit; and
a second comparison circuit coupled to the second sensing circuit,
wherein the first comparison circuit receives a feedback signal from the first sensing circuit and a reference voltage, and in accordance therewith, generates a first bias control signal to control the bias at the gate of the first bias transistor, and wherein the second comparison circuit receives a feedback signal from the second sensing circuit and the reference voltage, and in accordance therewith, generates a second bias control signal to control the bias at the gate of the second bias transistor.

### Claim 2 (depends on 1)

The mixer circuit of claim 1 further comprising an amplifier having at least one input, an output coupled to the gate of the first bias transistor, and a bias control input coupled to an output of the first comparison circuit.

### Claim 3 (depends on 1)

The mixer circuit of claim 1 wherein the first sensing circuit comprises a resistor coupled to the source of the first bias transistor.

### Claim 4 (depends on 1)

The mixer circuit of claim 1 further comprising a first low pass filter coupled between the first sensing circuit and the first comparison circuit.

### Claim 5 (depends on 1)

The mixer circuit of claim 1 wherein the first comparison circuit is a first amplifier coupled to receive the reference voltage and feedback signal.

### Claim 6 (depends on 5)

The mixer circuit of claim 5 wherein the first amplifier generates a current into a bias circuit of a second amplifier for changing the bias of an input signal at the gate of the first bias transistor.

### Claim 7 (depends on 1)

The mixer circuit of claim 1 wherein the first comparison circuit comprises first differential transistors having a first input coupled to the first sensing circuit and a second input coupled to the reference voltage.

### Claim 8 (depends on 1)

The mixer circuit of claim 1 further comprising an amplifier having at least one input, an output coupled to the gate of the second bias transistor, and a bias control input coupled to an output of the second comparison circuit.

### Claim 9 (depends on 1)

The mixer circuit of claim 1 further comprising a resistor coupled between the source of the first bias transistor and the source of the second bias transistor.

### Claim 10

A method of reducing offset in a mixer circuit, the method comprising;
receiving a first signal at the gate of a first transistor;
receiving a second signal at the gate of the second transistor, wherein the first and second signals are differential signals;
coupling a source of the first transistor to a source of the second transistor through a capacitor;
receiving a third signal at the gate of a first bias transistor, wherein the drain of the first bias transistor is coupled to the source of the first transistor;
receiving said third signal at the gate of a second bias transistor, wherein the drain of the second bias transistor is coupled to the source of the second transistor;
sensing a first bias current through the first bias transistor to generate a first feedback signal, and sensing a second bias current through the second bias transistor to generate a second feedback signal;
comparing the first feedback signal to a first reference voltage, and in accordance therewith, generating a first bias control signal and comparing the second feedback signal to a second reference voltage, and in accordance therewith, generating a second bias control signal; and
adjusting the first bias current using the first bias control signal, and adjusting the second bias current using the second bias control signal.

### Claim 11 (depends on 10)

The method of claim 10 further comprising low pass filtering the first and second bias control signals.

### Claim 12 (depends on 10)

The method of claim 10 wherein sensing a first bias current comprises coupling the first bias current at a source terminal of the first bias transistor through a resistor.

### Claim 13 (depends on 10)

The method of claim 10 further comprising amplifying the first and second bias control signals.

### Claim 14 (depends on 10)

The method of claim 10 further comprising translating the first bias control signal into a first current and coupling the first current to a first amplifier through a first current mirror and translating the second bias control signal into a second current and coupling the second current to a second amplifier through a second current mirror.

### Claim 15

A mixer circuit comprising:
first and second transistors coupled to receive a first differential input signal;
a capacitor coupled between a source of the first transistor and a source of the second transistor;
a third transistor coupled to provide bias current to the first transistor;
a fourth transistor coupled to provide bias current to the second transistor;
a first sense circuit coupled to sense current through the third transistor;
a second sense circuit coupled to sense current through the fourth transistor;
a first comparison circuit coupled to the first sense circuit and to a reference voltage, the first comparison circuit generating a first bias control signal; and
a second comparison circuit coupled to the second sense circuit and to a reference voltage, the second comparison circuit generating a second bias control signal; and
a first amplifier coupled to an input signal and providing the input signal to a gate of the third transistor,
a second amplifier coupled to the input signal and providing the input signal to a gate of the fourth transistor,
wherein the first amplifier receives the bias control signal on a bias control input and changes the level of offset of the input signal at the gate of the third transistor, and
wherein the second amplifier receives the second bias control signal on a bias control input and changes the level of offset of the input signal at the gate of the fourth transistor.

### Claim 16 (depends on 15)

The mixer circuit of claim 15 wherein the first sense circuit comprises a first resistor coupled to a source of the third transistor.

### Claim 17 (depends on 15)

The mixer circuit of claim 15 further comprising a low pass filter coupled between the first sense circuit and the bias control input of the first amplifier.

### Claim 18

An integrated circuit comprising:
a first transistor having a gate, a source, and a drain, wherein the gate of the first transistor is coupled to a first signal;
a second transistor having a gate, a source, and a drain, wherein the gate of the second transistor is coupled to a second signal and wherein the first and second signals are differential signals;
a capacitor coupled between the source of the first transistor and the source of the second transistor;
a first bias transistor having a gate, a source, and a drain, wherein the drain of the first bias transistor is coupled to the source of the first transistor;
a second bias transistor having a gate, a source, and a drain, wherein the drain of the second bias transistor is coupled to the source of the second transistor;
a first feedback loop having an input coupled to receive a third signal, and an output coupled to the gate of the first bias transistor; and
a second feedback loop having an input coupled to receive said third signal, and an output coupled to the gate of the second bias transistor.

### Claim 19 (depends on 18)

The integrated circuit of claim 18 wherein the first feedback loop comprises a comparison circuit.

### Claim 20 (depends on 18)

The integrated circuit of claim 18 wherein the first feedback loop comprises a low pass filter.

### Claim 21 (depends on 19)

The integrated circuit of claim 19 wherein the first feedback loop comprises a sensing circuit.

### Claim 22 (depends on 21)

The integrated circuit of claim 21 wherein the sensing circuit comprises a resistor.

### Claim 23 (depends on 19)

The integrated circuit of claim 19, the first and second feedback loops comprising:
a sensing circuit to sense a current, and in accordance therewith, generate a feedback signal;
a comparison circuit coupled to an output of the sensing circuit for comparing a reference voltage to the feedback signal, the comparison circuit generating a bias control signal; and
an amplifier circuit having an input coupled to receive said third signal and a bias control input coupled to receive said bias control signal for controlling the DC bias of the third signal at the output of said amplifier.

### Claim 24 (depends on 23)

The integrated circuit of claim 23 wherein the sensing circuit comprises a resistor.