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US 7,287,183 B2Granted
Electronic control unit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKohji Hashimoto, Katsuya Nakamoto, Yuki Iwagami, Akihiro Ishii
Life of this patent
Estimating the term…
Abstract
First and second control circuit sections that mutually communicate via a series-parallel converter comprise first and second adder-subtracter respectively. When any receiving error occurs in each control circuit section, a variation value 3 is added to the adder-subtracter on the receiving side. When data is normally received, a variation value 1 is subtracted from the adder-subtracter. Initial value of the adder-subtracter is set to 9. When a current value exceeds 11, first and second error detection signal is generated to carry out alarm display or initialization, and initialization and restart of the other-side control circuit section.
Claims18
An electronic control unit comprising:
- a first control circuit section which comprises:
- a program memory with input/output control means and communication control means with respect to external equipment,
- an operation processing memory,
- a main processing unit which cooperates with said program memory, and a first series-parallel converter;
- and
- a second control circuit section which comprises:
- a communication control circuit section which carries out a communication of a monitoring and control signal,
- a data memory, and
- a second series-parallel converter,
- wherein said electronic control unit is arranged such that serial communication of the monitoring and control signal is carried out mutually between said first control circuit section and said second control circuit section via said first series-parallel converter and second series-parallel converter,
- wherein said first control circuit section further comprises:
- first communication error determination means for determining presence or absence of any error of data received from said second control circuit section;
- first adding-subtracting means that performs a first operation on a first variation value when said first communication error determination means determines the absence of error, and performs a second operation on a second variation value when said first communication error determination means determines the presence of the error in order to carry out a first addition and subtraction compensation with respect to a first current value, and stops the first addition and subtraction compensation at a normal-side limit value when the determination of the absence of error continues;
- and
- first error occurrence definition means for generating an error detection signal when the first current value of said first adding-subtracting means exceeds an abnormal-side limit value as a result of an accumulation of said first and second variation values;
- and
- wherein said second control circuit section further comprises:
- second communication error determination means for determining the presence or absence of error of data received from said first control circuit section;
- second adding-subtracting means that performs the first operation on the first variation value when said second communication error determination means determines the absence of error, and performs the second operation on the second variation value when said second communication error determination means determines the presence of the error to carry out a second addition and subtraction compensation with respect to a second current value, and stops the second addition and subtraction compensation at the normal-side limit value when the determination of the absence of error continues;
- and
- second error occurrence definition means for generating an error detection signal when the second current value of said second adding-subtracting means exceeds the predetermined abnormal-side limit value as a result of an accumulation of said first and second variation values, and
- wherein the second variation value is set to be a value larger than said first variation value and smaller than a permitted accumulation value that is a difference between said abnormal-side limit value and said normal-side limit value;
- and operation stop or initiation restart of the said first control circuit section or said second control circuit section is carried out in response to an error detection signal generated by the said first error occurrence definition means or second error occurrence definition means.
20 more elements
An electronic control unit comprising:
- a first control circuit section comprising:
- a program memory with input/output control means and communication control means with respect to external equipment,
- an operation processing memory,
- a main processing unit cooperating with said program memory,
- a direct input interface circuit,
- a direct output interface circuit, and
- a first series-parallel converter;
- and
- a second control circuit section comprising:
- a communication control circuit section for carrying out communication of a monitoring and control signal,
- a data memory, and
- a second series-parallel converter,
- wherein said electronic control unit is arranged such that serial communication of a monitoring and control signal is carried out mutually between said first control circuit section and said second control circuit section via said first series-parallel converter and second series-parallel converter,
- wherein said main processing unit generates an output signal in response to a direct input signal having been inputted via said direct input interface circuit, an indirect input signal having been received by serial communication from the second series-parallel converter, which is provided in said second control circuit section, and a content of the program memory to drive an electrical load group connected to said direct output signal interface circuit;
- and transmits an indirect output signal to the second control circuit section via said first and second series-parallel converters;
- wherein said first control circuit section includes first receiving interval error determination means for determining that a receiving interval of a communication data to be regularly reported from said second control circuit section exceeds a first threshold value, and generating a first error detection signal;
- and
- said second control circuit section includes second receiving interval error determination means for determining that a receiving interval of a communication data to be regularly transmitted from said first control circuit section exceeds a second threshold value, and generating a second error detection signal;
- wherein one of said first control circuit section and said second control circuit section includes a watchdog timer that watches a watchdog clear signal, which said main processing unit generates, and generates a reset pulse signal when a pulse width of said watchdog clear signal exceeds a pulse width limit value, being a value smaller than said second threshold value;
- and error occurrence storage means for storing an error detection signal or a reset pulse signal, and bringing annunciation means in operation when said first and second error detection signal is generated, or when said watchdog timer generates a reset pulse signal;
- and
- wherein said main processing unit is initialized and restarted when said watchdog timer generates a reset pulse signal or when said second error detection signal is generated;
- and said communication control circuit section of said second control circuit section is initialized and restarted when said watchdog timer generates a reset pulse signal or said first error detection signal is generated.
20 more elements
Dependencies are inferred from the claim text.