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US 7,285,812 B2Granted
Vertical transistors
AssigneeMicron Technology, Inc.
InventorsSanh Dang Tang, Gordon A. Haller
Life of this patent
Estimating the term…
Abstract
Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the lower active area. Vertical transistor pillars can be formed from epitaxial silicon or etched from bulk silicon. Memory cells can be formed by creating a cell capacitor electrically connected to each transistor pillar.
Claims19
A memory array comprising:
- a substrate having a plurality of ridges separating a plurality of trenches, each ridge extending from a bottom level of the trenches to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, and each trench extending from the bottom level to the shoulder;
- a bit line buried below the shoulder within each trench;
- a plurality of transistor pillars over each of the plurality of ridges, each transistor pillar extending upwardly from the shoulder of the ridge, wherein the transistor pillars include an upper active area;
- a plurality of lower active areas in the upper surface of each of the plurality of ridges, wherein one of the lower active areas is below each transistor pillar;
- a bit line link within each trench connecting each lower active area and the bit line;
- and
- a plurality of word lines, wherein each word line contacts a row of transistor pillars and crosses over at least two of the plurality of ridges.
4 more elements
A vertical transistor for an integrated circuit, comprising:
- a buried bit line within a trench in a bulk semiconductor substrate;
- a transistor pillar formed over a ridge in the semiconductor substrate, wherein the ridge is adjacent to the trench and extends from a bottom level of the trench to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, wherein the transistor pillar extends upwardly from the shoulder of the ridge, wherein the trench extends from the bottom level to the shoulder, and wherein the buried bit line is below the shoulder within the trench;
- a bit line link in the trench connecting the buried bit line to a lower active area in the ridge;
- and
- a conductive gate surrounding the transistor pillar.
2 more elements
Dependencies are inferred from the claim text.