Finite state machine interface has arbitration structure to store command generated by internal circuits during evaluation phase of state machine for FLASH EEPROM device

A device comprising:

• a plurality of internal circuits;
• and
• an interface for said plurality of internal circuits and external circuits and comprising
• a finite state machine for managing asynchronous and independent interactions between said plurality of internal circuits and external circuits, said finite state machine functioning based upon a unique clock and a unique reset, and
• an arbitration circuit connected to said finite state machine for receiving input signals for said finite state machine, and for storing the input signals generated by said plurality of internal circuits when said finite state machine is performing an evaluation.

A non-volatile memory device comprising:

• a plurality of digital circuits;
• and
• a command interpreter circuit for recognizing operations required from the non-volatile memory device through command codes and for implementing a handshake with said plurality of digital circuits, said command interpreter circuit comprising
• a finite state machine for managing asynchronous and independent interactions between said plurality of digital circuits and external circuits, said finite state machine functioning based upon a unique clock and a unique reset, and an arbitration circuit connected to said finite state machine for receiving the command codes for said finite state machine, and for storing the command codes generated by said plurality of digital circuits when said finite state machine is performing an evaluation.

A method for managing a finite state machine through an input arbitration circuit that stores commands to be executed, and provides a clock to the finite state machine, the method comprising:

• a) for each new command, verifying whether it is received while the finite state machine is carrying out a previous command;
• b) if step a) is negative, then issuing the new command to the finite state machine in real time, and restarting a new cycle from step a);
• c) if step a) is positive, then verifying whether the new command can be ignored;
• and
• d) if step c) is negative, then storing the new command in the input arbitration circuit, waiting for the finite state machine to end execution of the previous command, issuing a deferred command to the finite state machine, and erasing the new command from the input arbitration circuit.