US 7,284,027 B2Granted

Method and apparatus for high speed calculation of non-linear functions and networks using non-linear function calculations for digital signal processing

AssigneeQSigma, Inc.

InventorsEarle Willis Jennings, III, George Landers

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Abstract

The invention includes apparatus and methods for high-speed calculation of non-linear functions based upon a shifted adder and a offset generator. Various implementations may preferably include a input preprocessor and/or an output post processor. The invention includes a family of core cells built from instances of these calculators providing an upward, functionally compatible, extension to a family of Application Specific Integrated Circuit (ASIC) core cells. All of these core cells consistently provide the ability to perform high speed DSP tasks including Fast Fourier Transforms (FFTs), Finite Impulse Response (FIR) filters and Infinite Impulse Response (IIR) filters. The core cells built from the calculators can concurrently perform many non-linear function calculations. The core cells can switch between tasks every clock cycle.

Claims43

Dependent claims

A complex multiplier providing a complex product of a first complex input, includes a first component input collection comprising an A1R and an A1I, and a second complex number defined by a LogA2R and an LogA2I, comprising:

a collection of logarithm calculators, receiving said first complex input to create a first complex log version number;
a collection of adders, adding said first complex log version number to said LogA2R to create a LogA1RA2R and a LogA1IA2R while adding said first complex log version number to said LogA2I to create a LogA1IA2I and a LogA1RA2I;
a collection of exponential calculators, exponentiating each member of a complex log component collection to create a corresponding member of a complex numeric component collection;
and
wherein said complex log component collection includes said LogA1RA2R and said LogA1IA2I, said LogA1IA2R and said LogA1RA2I;
wherein said complex numeric component collection includes an A1RA2R, an A1IA2I, an A1IA2R, and an A1RA2I;
wherein said complex product includes an A12R and an A12I;
wherein said first complex log version number includes a LogA1R and a LogA1I;
wherein whenever said A1R equals zero, said A1RA2R equals said zero and said A1RA2I equals said zero, further comprising:
wherein whenever said A1R equals zero, said LogA1R indicates negative infinity;
wherein whenever said LogA1R indicates said negative infinity, said LogA1RA2R indicates said negative infinity and said LogA1RA2I indicates said negative infinity;
wherein whenever said LogA1RA2R indicates said negative infinity, said A1RA2R equals zero;
and
wherein whenever said LogA1RA2I indicates said negative infinity, said A1RA2I equals zero;
wherein whenever said A1I equals said zero, said A1IA2R equals said zero and said A1IA2R equals said zero, further comprising:
wherein whenever said A1I equals zero, said LogA1I indicates said negative infinity;
wherein whenever said LogA1I indicates said negative infinity, said LogA1IA2R indicates said negative infinity and said LogA1IA2I indicates said negative infinity;
wherein whenever said LogA1IA2R indicates said negative infinity, said A1IA2R equals zero;
and
wherein whenever said LogA1IA2I indicates said negative infinity, said A1IA2I equals zero.

17 more elements

An apparatus providing a complex product of a first complex input and a second complex number defined by a Log A2R and an Log A2I;

wherein said first complex input includes a first component input collection comprising an A1R and an A1I;
wherein said first complex log version number includes a Log A1R and a Log A1I;
wherein said apparatus, comprising:
means for receiving said first complex input to create a first complex log version number, further comprising:
means for whenever said A1R equals zero, said Log A1R indicates negative infinity;
and
means for whenever said A1I equals zero, said Log A1I indicates negative infinity;
means for adding said first complex log version number to said Log A2R of said second complex number to create a Log A1RA2R and a Log A1IA2I while adding said first complex log version number to said Log A2I of said second complex number to create a Log A1IA2R and a Log A1RA2I, further comprising:
means for whenever said Log A1R indicates said negative infinity, said Log A1RA2R indicates said negative infinity and said Log A1RA2I indicates said negative infinity;
and
means for whenever said Log A1I indicates said negative infinity, said Log A1IA2R indicates said negative infinity and said Log A1IA2I indicates said negative infinity;
means for exponentiating each of member of a complex log component collection to create a corresponding member of a complex numeric component collection including an A1RA2R, an A1IA2I, an A1IA2R, and an A1RA2I, comprising:
means for whenever said Log A1RA2R indicates said negative infinity, said A1RA2R equals zero;
means for whenever said Log A1RA2I indicates said negative infinity, said A1RA2I equals zero;
means for whenever said Log A1IA2R indicates said negative infinity, said A1IA2R equals zero;
and
means for whenever said Log A1IA2I indicates said negative infinity, said A1IA2I equals zero;
wherein said complex product includes an A12R and an A12I;
wherein said A12R equals said A1RA2R minus said A1IA2I;
and
wherein said A12I equals said A1IA2R plus said A1RA2I.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/226,735Filed 22 Aug 2002 · continuation in part
Priority: 15 May 2000
Published: US 2003/0041083 A127 Feb 2003
Granted: 16 Oct 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 1/0307
Working, at least partly, by table look-up: logarithmic or exponential functions
G06F 7/4806
Using non-contact-making devices, e.g. tube, solid state device; using unspecified devices: computations with complex numbers
G06F 7/57
Using non-contact-making devices, e.g. tube, solid state device; using unspecified devices: arithmetic logic units [ALU], i.e. arrangements or…
G06F 30/30
Computer-aided design [CAD]: circuit design

Family

Application60/204,113Us provisional application · filed 15 May 2000
Application60/215,894Us provisional application · filed 5 Jul 2000
Application60/217,353Us provisional application · filed 11 Jul 2000
Application60/231,873Us provisional application · filed 12 Sep 2000
Application60/261,066Us provisional application · filed 11 Jan 2001
Application60/282,093Us provisional application · filed 6 Apr 2001
PCT/US01/15541Parent of this continuation-in-part · filed 14 May 2001
Application60/314,411Us provisional application · filed 22 Aug 2001
Application60/325,093Us provisional application · filed 25 Sep 2001
Application60/365,416Us provisional application · filed 18 Mar 2002
Application10/155,502Parent of this continuation-in-part · filed 23 May 2002
Application60/402,346Us provisional application · filed 9 Aug 2002
US 2003/0041083 A1Pre-grant publication · published 27 Feb 2003
US 2003/0233219 A1Published application
US 7,284,027 B2This patent

From the US filing history. Foreign family members aren’t listed.