# US 7,283,105 B2 · Microdisplay and interface on single chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,283,105 B2 - Document ID: US7283105B2 - Status: Granted - Kind: B2 - Application number: 10/831,545 - Filed: 2004-04-23 - Published: 2004-12-30 - Granted: 2007-10-16 - Earliest claimed: 2003-04-24 - Assignees: Displaytech, Inc. - Inventors: James M. Dallas; David B. Hollenbeck; Per Harold Larsen; Rainer M. Malzbender; Earle R. Vickery, III; Michael Wayne Yee - Web page: https://patentgrep.com/patent/US7283105B2 ## CPC - G09G 5/00: Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators (image data processing or generation, in general G06T) - G02F 1/133553: {Reflecting elements (associated to illuminating devices G02F1/133605)} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/2003: {Display of colours (specific for liquid crystal displays G09G3/3607)} - G09G 3/2014: {by modulation of the duration of a single pulse during which the logic level remains constant} - G09G 3/2088: {with use of a plurality of processors, each processor controlling a number of individual elements of the matrix} - G09G 3/3651: {using multistable liquid crystals, e.g. ferroelectric liquid crystals} - G11C 11/417: for memory cells of the field-effect type - G09G 3/2059: {using error diffusion} - G09G 3/3413: {Details of control of colour illumination sources} - G09G 3/3685: {Details of drivers for data electrodes} - G09G 3/3688: {suitable for active matrices only} - G09G 5/02: characterised by the way in which colour is displayed {(details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607)} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0809: Several active elements per pixel in active matrix panels - G09G 2300/0857: Static memory circuit, e.g. flip-flop - G09G 2310/0221: with use of split matrices (G09G3/3644 and G09G3/3666 take precedence) - G09G 2310/0235: Field-sequential colour display - G09G 2310/0259: with use of an analog or digital ramp generator in the column driver or in the pixel circuit - G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters - G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current - G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit - G09G 2310/061: for resetting or blanking - G09G 2320/041: Temperature compensation - G09G 2320/0666: for control of colour parameters, e.g. colour temperature - G09G 2330/021: Power management, e.g. power saving - G09G 2340/02: Handling of images in compressed format, e.g. JPEG, MPEG - G09G 2340/0407: Resolution change, inclusive of the use of different resolutions for different screen areas - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A microdisplay having interface circuitry on the same silicon backplane to allow it to receive digital images and video in a variety of formats and convert same to field sequential color signals for generation of full color images. It includes column data processors having a comparator for each block of N-columns of pixels. Image data is double-buffered in SRAM memory cells located beneath the pixel electrodes, but not within each pixel. The stored data is logically associated with each pixel via the column data processors. Image compression is accomplished by converting RGB data to a variant of YUV data and sampling the color components of the converted data less frequently than the luminance components. The SRAM image buffer consumes a reduced amount of power. A temperature compensation scheme allows the temperature of the microdisplay to be sensed and the drive voltage to the pixel electrodes to be varied in response thereto. ## Claims ### Claim 1 A microdisplay system for displaying image data, comprising: a microdisplay having an array of pixels switchable between different display states to produce a gray-scale image, the microdisplay residing on a semiconductor substrate, each pixel having circuitry in and circuitry operatively associated therewith, the circuitry in and operatively associated with each pixel being digital circuitry including a plurality of transistors, there being less than 700 transistors in this circuitry; and a digital interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format; wherein the digital interface device converts RGB data to a data format having a luminance component and at least two chroma components. ### Claim 2 (depends on 1) A microdisplay system as defined in claim 1, wherein the microdisplay includes memory cells resident therein to store the image data in the data format having a luminance component and at least two chroma components. ### Claim 3 (depends on 2) A microdisplay system as defined in claim 2, wherein luminance data is stored for every individual pixel and chroma data is stored for groups of a plurality of pixels. ### Claim 4 (depends on 1) A microdisplay system as defined in claim 1, wherein the microdisplay displays image data by sequentially displaying fields of a first color, a second color, and a third color. ### Claim 5 (depends on 1) A microdisplay system as defined in claim 1, wherein the microdisplay includes memory cells for storing image data to be displayed, the memory cells being distributed throughout the microdisplay, wherein each pixel includes a reflective pixel electrode and the reflective pixel electrodes lie in a first plane, and wherein the distributed memory cells lie in a second plane that is and parallel to the first plane, and further wherein the orthogonal projection onto the second plane of at least some of the reflective pixel electrodes covers memory cells that store image information for other reflective pixel electrodes. ### Claim 6 (depends on 1) A microdisplay system as defined in claim 1, wherein the microdisplay includes dual memory buffers for storing two consecutive frames of image data for each pixel. ### Claim 7 (depends on 1) A microdisplay system as defined in claim 1, wherein there are less than 135 transistors in this circuitry. ### Claim 8 (depends on 1) A microdisplay system as defined in claim 1, wherein new image data is provided in a series of frames of image data and the time from receiving the beginning of one frame of image data to the time of receiving the beginning of the next subsequent frame of image data is referred to as the frame time, wherein the microdisplay displays gray-scale images during a majority of the frame time for each frame. ### Claim 9 A microdisplay system for displaying image data, comprising: a microdisplay having an array of pixels switchable between different display states to produce a gray-scale image, the microdisplay residing on a semiconductor substrate, each pixel having circuitry in and circuitry operatively associated therewith, the circuitry in and operatively associated with each pixel being digital circuitry including a plurality of transistors, there being less than 700 transistors in this circuitry; wherein the array of pixels in the microdisplay is arranged in rows and a first portion of the rows are in one group and a second portion of the rows are in a second group, and further wherein the pixels of one of the first and second group are updated with image information from a top row to a bottom row while the pixels of the other of the first and second group are updated with image information from a bottom row to a top row. ### Claim 10 (depends on 9) A microdisplay system as defined in claim 9, wherein the microdisplay displays image data by sequentially displaying fields of a first color, a second color, and a third color. ### Claim 11 (depends on 9) A microdisplay system as defined in claim 9, wherein the microdisplay includes memory cells for storing image data to be displayed, the memory cells being distributed throughout the microdisplay, wherein each pixel includes a reflective pixel electrode and the reflective pixel electrodes lie in a first plane, and wherein the distributed memory cells lie in a second plane that is and parallel to the first plane, and further wherein the orthogonal projection onto the second plane of at least some of the reflective pixel electrodes covers memory cells that store image information for other reflective pixel electrodes. ### Claim 12 (depends on 9) A microdisplay system as defined in claim 9, wherein the microdisplay includes dual memory buffers for storing two consecutive frames of image data for each pixel. ### Claim 13 (depends on 9) A microdisplay system as defined in claim 9, wherein there are less than 135 transistors in this circuitry. ### Claim 14 (depends on 9) A microdisplay system as defined in claim 9, the system further including an interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format. ### Claim 15 (depends on 14) A microdisplay system as defined in claim 14, wherein the first format is a standard video signal. ### Claim 16 (depends on 14) A microdisplay system as defined in claim 14, wherein the first format includes RGB data for a pixel, followed by RGB data for a second pixel, and continuing in sequence until an entire row of RGB pixel data has been provided, followed by another row of RGB pixel data. ### Claim 17 (depends on 14) A microdisplay system as defined in claim 14, wherein the second format includes sequential fields of a first color, a second color, and a third color. ### Claim 18 (depends on 9) A microdisplay system as defined in claim 9, wherein new image data is provided in a series of frames of image data and the time from receiving the beginning of one frame of image data to the time of receiving the beginning of the next subsequent frame of image data is referred to as the frame time, wherein the microdisplay displays gray-scale images during a majority of the frame time for each frame. ### Claim 19 A microdisplay system for displaying image data, comprising: a microdisplay having an array of pixels switchable between different display states to produce a gray-scale image, the microdisplay residing on a semiconductor substrate, each pixel having circuitry in and circuitry operatively associated therewith, the circuitry in and operatively associated with each pixel being digital circuitry including a plurality of transistors, there being less than 700 transistors in this circuitry; wherein a representation of the image data is stored in circuitry residing on the semiconductor substrate; wherein the microdisplay includes centralized timing circuitry that services a plurality of pixels and, based on a ramp counter signal and the stored representation of the image data for each pixel of the plurality of pixels, a separate pixel state signal for each pixel is generated and sent to each pixel. ### Claim 20 (depends on 19) A microdisplay system as defined in claim 19, wherein the microdisplay displays image data by sequentially displaying fields of a first color, a second color, and a third color. ### Claim 21 (depends on 19) A microdisplay system as defined in claim 19, wherein the microdisplay includes memory cells for storing image data to be displayed, the memory cells being distributed throughout the microdisplay, wherein each pixel includes a reflective pixel electrode and the reflective pixel electrodes lie in a first plane, and wherein the distributed memory cells lie in a second plane that is and parallel to the first plane, and further wherein the orthogonal projection onto the second plane of at least some of the reflective pixel electrodes covers memory cells that store image information for other reflective pixel electrodes. ### Claim 22 (depends on 19) A microdisplay system as defined in claim 19, wherein the microdisplay includes dual memory buffers for storing two consecutive frames of image data for each pixel. ### Claim 23 (depends on 19) A microdisplay system as defined in claim 19, wherein there are less than 135 transistors in this circuitry. ### Claim 24 (depends on 19) A microdisplay system as defined in claim 19, the system further including an interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format. ### Claim 25 (depends on 24) A microdisplay system as defined in claim 24, wherein the first format is a standard video signal. ### Claim 26 (depends on 24) A microdisplay system as defined in claim 24, wherein the first format includes RGB data for a pixel, followed by RGB data for a second pixel, and continuing in sequence until an entire row of RGB pixel data has been provided, followed by another row of RGB pixel data. ### Claim 27 (depends on 24) A microdisplay system as defined in claim 24, wherein the second format includes sequential fields of a first color, a second color, and a third color. ### Claim 28 (depends on 19) A microdisplay system as defined in claim 19, wherein new image data is provided in a series of frames of image data and the time from receiving the beginning of one frame of image data to the time of receiving the beginning of the next subsequent frame of image data is referred to as the frame time, wherein the microdisplay displays gray-scale images during a majority of the frame time for each frame. ### Claim 29 A microdisplay system for displaying image data, comprising: a microdisplay having an array of pixels switchable between different display states to produce a gray-scale image, the microdisplay residing on a semiconductor substrate, each pixel having circuitry in and circuitry operatively associated therewith, the circuitry in and operatively associated with each pixel being digital circuitry including a plurality of transistors, there being less than 700 transistors in this circuitry; wherein the digital circuitry of each pixel in the microdisplay includes memory cells for storing image data to be displayed, the memory cells being distributed throughout the microdisplay, wherein the distributed memory cells are co-located with the pixel array but are not physically associated with particular pixels in the pixel array, and further wherein each pixel includes a reflective pixel electrode and the reflective pixel electrodes lie in a first plane, and wherein the distributed memory cells lie in a second plane that is parallel to the first plane, and further wherein the orthogonal projection onto the second plane of at least some of the reflective pixel electrodes covers memory cells that store image information for other reflective pixel electrodes. ### Claim 30 (depends on 29) A microdisplay system as defined in claim 29, wherein the microdisplay displays image data by sequentially displaying fields of a first color, a second color, and a third color. ### Claim 31 (depends on 29) A microdisplay system as defined in claim 29, wherein the microdisplay includes dual memory buffers for storing two consecutive frames of image data for each pixel. ### Claim 32 (depends on 29) A microdisplay system as defined in claim 29, wherein there are less than 135 transistors in this circuitry. ### Claim 33 (depends on 29) A microdisplay system as defined in claim 29, the system further including an interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format. ### Claim 34 (depends on 33) A microdisplay system as defined in claim 33, wherein the first format is a standard video signal. ### Claim 35 (depends on 33) A microdisplay system as defined in claim 33, wherein the first format includes RGB data for a pixel, followed by RGB data for a second pixel, and continuing in sequence until an entire row of RGB pixel data has been provided, followed by another row of RGB pixel data. ### Claim 36 (depends on 33) A microdisplay system as defined in claim 33, wherein the second format includes sequential fields of a first color, a second color, and a third color. ### Claim 37 (depends on 29) A microdisplay system as defined in claim 29, wherein new image data is provided in a series of frames of image data and the time from receiving the beginning of one frame of image data to the time of receiving the beginning of the next subsequent frame of image data is referred to as the frame time, wherein the microdisplay displays gray-scale images during a majority of the frame time for each frame. ### Claim 38 A microdisplay system for displaying image data, comprising: a microdisplay having an array of pixels switchable between different display states to produce a gray-scale image, the microdisplay residing on a semiconductor substrate, each pixel having circuitry in and circuitry operatively associated therewith, the circuitry in and operatively associated with each pixel being digital circuitry including a plurality of transistors, there being less than 700 transistors in this circuitry; and a digital interface device also residing on said semiconductor substrate, the interface device accepting image data in standard video format in a first order, and wherein the microdisplay displays image data in a second order by sequentially displaying fields of a first color, a second color, and a third color; wherein each pixel has a display surface, each pixel having at least one memory register operatively associated therewith that contains information relating to a future display state of the pixel; and wherein the surface area on the semiconductor substrate consumed by each pixel and the at least one memory register operatively associated with that pixel is less than 1000 square microns. ### Claim 39 (depends on 38) A microdisplay system as defined in claim 38, wherein the microdisplay displays image data by sequentially displaying fields of a first color, a second color, and a third color. ### Claim 40 (depends on 38) A microdisplay system as defined in claim 38, wherein the microdisplay includes memory cells for storing image data to be displayed, the memory cells being distributed throughout the microdisplay, wherein each pixel includes a reflective pixel electrode and the reflective pixel electrodes lie in a first plane, and wherein the distributed memory cells lie in a second plane that is and parallel to the first plane, and further wherein the orthogonal projection onto the second plane of at least some of the reflective pixel electrodes covers memory cells that store image information for other reflective pixel electrodes. ### Claim 41 (depends on 38) A microdisplay system as defined in claim 38, wherein the microdisplay includes dual memory buffers for storing two consecutive frames of image data for each pixel. ### Claim 42 (depends on 38) A microdisplay system as defined in claim 38, wherein there are less than 135 transistors in this circuitry. ### Claim 43 (depends on 38) A microdisplay system as defined in claim 38, the system further including an interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format. ### Claim 44 (depends on 43) A microdisplay system as defined in claim 43, wherein the first format is a standard video signal. ### Claim 45 (depends on 43) A microdisplay system as defined in claim 43, wherein the first format includes RGB data for a pixel, followed by RGB data for a second pixel, and continuing in sequence until an entire row of RGB pixel data has been provided, followed by another row of RGB pixel data. ### Claim 46 (depends on 43) A microdisplay system as defined in claim 43, wherein the second format includes sequential fields of a first color, a second color, and a third color. ### Claim 47 (depends on 38) A microdisplay system as defined in claim 38, wherein new image data is provided in a series of frames of image data and the time from receiving the beginning of one frame of image data to the time of receiving the beginning of the next subsequent frame of image data is referred to as the frame time, wherein the microdisplay displays gray-scale images during a majority of the frame time for each frame. ### Claim 48 A microdisplay system for displaying image data, comprising: a microdisplay having an array of pixels switchable between different display states to produce a gray-scale image, the microdisplay residing on a semiconductor substrate, each pixel having circuitry in and circuitry operatively associated therewith, the circuitry in and operatively associated with each pixel being digital circuitry including a plurality of transistors, there being less than 700 transistors in this circuitry; an interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format; wherein the interface device converts RGB data to a data format having a luminance component and at least two chroma components. ### Claim 49 (depends on 48) A microdisplay system as defined in claim 48, wherein the microdisplay includes memory cells resident therein to store the image data in the data format having a luminance component and at least two chroma components. ### Claim 50 (depends on 49) A microdisplay system as defined in claim 49, wherein luminance data is stored for every individual pixel and chroma data is stored for groups of a plurality of pixels. ### Claim 51 (depends on 48) A microdisplay system as defined in claim 48, wherein the microdisplay displays image data by sequentially displaying fields of a first color, a second color, and a third color. ### Claim 52 (depends on 48) A microdisplay system as defined in claim 48, wherein the microdisplay includes memory cells for storing image data to be displayed, the memory cells being distributed throughout the microdisplay, wherein each pixel includes a reflective pixel electrode and the reflective pixel electrodes lie in a first plane, and wherein the distributed memory cells lie in a second plane that is and parallel to the first plane, and further wherein the orthogonal projection onto the second plane of at least some of the reflective pixel electrodes covers memory cells that store image information for other reflective pixel electrodes. ### Claim 53 (depends on 48) A microdisplay system as defined in claim 48, wherein the microdisplay includes dual memory buffers for storing two consecutive frames of image data for each pixel. ### Claim 54 (depends on 48) A microdisplay system as defined in claim 48, wherein there are less than 135 transistors in this circuitry. ### Claim 55 (depends on 48) A microdisplay system as defined in claim 48, wherein new image data is provided in a series of frames of image data and the time from receiving the beginning of one frame of image data to the time of receiving the beginning of the next subsequent frame of image data is referred to as the frame time, wherein the microdisplay displays gray-scale images during a majority of the frame time for each frame. ### Claim 56 A microdisplay system for displaying image data, comprising: a microdisplay having an array of pixels switchable between different display states to produce a gray-scale image, the microdisplay residing on a semiconductor substrate, each pixel having less than 700 transistors in and operatively associated therewith; and a digital interface device also residing on said semiconductor substrate, the interface device accepting input image data organized into sequential frames in standard video format in a first order, and wherein the microdisplay displays image data in a second order by sequentially displaying fields of a first color, a second color, and a third color, wherein in any given displayed field the displayed image is based on a single frame of input image data. ### Claim 57 (depends on 56) A microdisplay system as defined in claim 56, wherein the microdisplay includes memory cells for storing image data to be displayed, the memory cells being distributed throughout the microdisplay, wherein each pixel includes a reflective pixel electrode and the reflective pixel electrodes lie in a first plane, and wherein the distributed memory cells lie in a second plane that is and parallel to the first plane, and further wherein the orthogonal projection onto the second plane of at least some of the reflective pixel electrodes covers memory cells that store image information for other reflective pixel electrodes. ### Claim 58 (depends on 56) A microdisplay system as defined in claim 56, wherein said first color, second color, and third color are red, green, and blue (RGB). ### Claim 59 (depends on 58) A microdisplay system as defined in claim 58, wherein the standard video format includes RGB data for a pixel, followed by RGB data for a second pixel, and continuing in sequence until an entire row of RGB pixel data has been provided, followed by another row of RGB pixel data. ### Claim 60 (depends on 56) A microdisplay system as defined in claim 56, wherein the microdisplay includes dual memory buffers for storing representations of two consecutive frames of image data for each pixel. ### Claim 61 (depends on 56) A microdisplay system as defined in claim 56, wherein there are less than 600 transistors in and operatively associated with each pixel. ### Claim 62 (depends on 56) A microdisplay system as defined in claim 56, wherein there are less than 500 transistors in and operatively associated with each pixel. ### Claim 63 (depends on 56) A microdisplay system as defined in claim 56, wherein there are less than 400 transistors in and operatively associated with each pixel. ### Claim 64 (depends on 56) A microdisplay system as defined in claim 56, wherein there are less than 300 transistors in and operatively associated with each pixel. ### Claim 65 (depends on 56) A microdisplay system as defined in claim 56, wherein there are less than 200 transistors in and operatively associated with each pixel. ### Claim 66 (depends on 56) A microdisplay system as defined in claim 56, wherein there are less than 160 transistors in and operatively associated with each pixel. ### Claim 67 (depends on 56) A microdisplay system as defined in claim 56, wherein there are less than 150 transistors in and operatively associated with each pixel. ### Claim 68 (depends on 56) A microdisplay system as defined in claim 56, wherein there are less than 140 transistors in and operatively associated with each pixel. ### Claim 69 (depends on 56) A microdisplay system as defined in claim 56, wherein there are less than 135 transistors in and operatively associated with each pixel. ### Claim 70 (depends on 56) A microdisplay system as defined in claim 56, wherein a representation of the image data is stored in the microdisplay and the microdisplay includes centralized timing circuitry that services a plurality of pixels and, based on a ramp counter signal and the stored representation of the image data for each pixel of the plurality of pixels, a separate pixel state signal for each pixel is generated and sent to each pixel.