Power LDMOS transistor

A lateral metal-oxide-semiconductor transistor device comprising:

• a highly doped semiconductor substrate having a N conductivity type and having a lightly doped epitaxial layer thereon having an upper surface;
• source and drain regions of the N conductivity type formed in the epitaxial layer proximate the upper surface, said source and drain regions being spaced from one another and having a channel region of a P conductivity type formed therebetween in said epitaxial layer, said channel region extending under said source region;
• a conductive gate formed over a gate dielectric layer formed over said channel region and partially overlapping said source and drain regions;
• at least one buffer layer having a dopant concentration equal to or greater than said channel region formed between said channel region and said substrate;
• a drain contact electrically connecting said drain region to said substrate and spaced from said channel region comprising:
• a first trench formed from the upper surface of said epitaxial layer to said substrate and having a side wall along said epitaxial layer;
• a highly doped region of said N conductivity type formed along said side wall of the first trench;
• and
• a drain plug in said first trench adjacent said highly doped region;
• an insulating layer extending along sidewalls of said conductive gate, over said conductive gate and over said drain region, said insulating layer comprising a first portion over said drain region and a second portion over said drain plug, said second portion being thicker than said first portion;
• and
• a source contact electrically connected to said source region and providing an electrical short between the source region and the channel region, said source contact comprising a layer of conductive material deposited over said insulating layer and in a second trench formed adjacent said source and channel regions and extending into said channel region, wherein said second trench is formed partially through said epitaxial layer such that a bottom surface thereof is spaced from an upper surface of said substrate.

A lateral metal-oxide-semiconductor power transistor device comprising:

• a substrate having a first conductivity type having a lightly doped epitaxial layer thereon having an upper surface;
• source and drain regions of the first conductivity type formed in the epitaxial layer proximate the upper surface, said source and drain regions being spaced from one another and having a channel region of a second conductivity type formed therebetween in said epitaxial layer, said channel region extending under said source region;
• a conductive gate formed over a gate dielectric layer formed over said channel region and partially overlapping said source and drain regions;
• at least one buffer layer having a dopant concentration equal to or greater than said channel region formed between said channel region and said substrate;
• a drain contact electrically connecting said drain region to said substrate and spaced from said channel region comprising a highly doped vertical implant region of said first conductivity type formed in said epitaxial layer;
• a source contact electrically connected to said source region and providing an electrical short between the source region and the channel region, wherein the source contact is formed at least in part in a trench formed in said epitaxial layer, wherein a bottom surface of said trench is spaced from an upper surface of said substrate;
• and
• an insulating layer formed between said conductive gate and said source contact.

A lateral metal-oxide-semiconductor transistor device comprising:

• a highly doped substrate having a first conductivity type and having an epitaxial layer formed thereon;
• source and drain implant regions of the first conductivity type formed in the epitaxial layer, said source and drain regions being spaced from one another and having a channel region of a second conductivity type formed therebetween in said epitaxial layer, said channel region extending under said source region;
• a conductive gate formed over the channel region;
• a drain contact electrically connecting said drain region to said substrate through the epitaxial layer;
• an insulating layer formed over said conductive gate and on an upper surface of said epitaxial layer;
• a source metal layer deposited over said insulating layer and forming a source contact providing an electrical short between the source region and the channel region;
• and
• wherein said insulating layer comprises a first portion defined between said source metal layer and said drain implant region and a second portion defined between said drain plug and said source metal layer, wherein said second portion is thicker than said first portion.

A lateral metal-oxide-semiconductor transistor device comprising:

• a non-epitaxial, highly doped substrate having a first conductivity type;
• an epitaxial layer having an upper surface and a lower surface formed on said substrate and having an implant doping profile, said implant doping profile comprising:
• source and drain implant regions of the first conductivity type formed proximate the upper surface of the epitaxial layer and spaced from one another,
• a body implant region comprising a channel region of a second conductivity type formed therebetween, said channel region extending under said source implant region;
• a first implant region having said second conductivity type implanted proximate to and underneath said channel region, said first implant region having a dopant concentration equal to or greater than a dopant concentration of said channel region, and
• a second implant region having said first conductivity type implanted below said first implant region;
• a conductive gate and a gate dielectric layer formed over the channel region;
• a drain contact electrically connecting said drain implant region to said substrate through the epitaxial layer;
• and
• a source contact electrically connected to said source region and providing an electrical short between the source region and the channel region.