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US 7,269,212 B1Granted
Low-latency equalization in multi-level, multi-line communication systems
AssigneeRambus Inc.
InventorsPak Shing Chau, Haw-Jyh Liaw, Jun Kim, Jared L. Zerbe
Life of this patent
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Abstract
Low-latency equalization mechanisms for multi-PAM communication systems are disclosed that reduce delay and complexity in signal correction mechanisms. The equalization mechanisms tap into input signals for a multi-PAM signal driver, and compensate for attenuation along a signal transmission line, crosstalk between adjacent lines, and signal reflections due to impedance discontinuities along the line.
Claims29
A communication system comprising:
- a first printed circuit board;
- a conductive path affixed to the printed circuit board;
- a driver circuit affixed to the first printed circuit board and coupled to the conductive path to output onto the conductive path a signal having a voltage level that varies in time between at least three distinct levels representative of at least three distinct digital values, the driver circuit including an equalization circuit to adjust the voltage level of the signal output by the driver circuit at a first time according to a digital value represented by the signal at a previous time;
- and
- a receiver circuit affixed to the first printed circuit board and coupled to receive the signal from the conductive path to determine which of the at least three distinct digital values is represented by the signal at a given time.
2 more elements
A communication system comprising:
- a main driver adapted to convert a plurality of binary input signals into a main signal that shifts over time between a plurality of signal levels representing respective ones of at least three logical states;
- and
- an equalization mechanism containing an auxiliary driver adapted to receive said plurality of binary input signals and to generate an equalization signal, said equalization signal being combined with the main signal to form an output signal in which a respective transition between two different signal levels is overdriven by an amount depending on the two different signal levels.
A communication system comprising:
- a signaling device configured to produce a set of signal levels representing a set of at least three logical states, said device including a main driver adapted to convert a plurality of binary input signals into an output signal that shifts over time between said signal levels to shift between said at least three logical states;
- and
- an equalization mechanism containing an auxiliary driver that is substantially proportional to said main driver, said equalization mechanism adapted to receive said plurality of binary input signals and generate a set of at least three equalization signals based on said plurality of binary input signals;
- wherein for each of said signal levels, an activation level of said main driver and an activation level of said auxiliary driver sum to equal N.
1 more element
A communication system comprising:
- a signaling device configured to produce a set of signal levels representing a set of at least three logical states, said device including a main driver adapted to convert a plurality of binary input signals into an output signal that shifts over time between said signal levels to shift between said at least three logical states;
- and
- an equalization mechanism containing an auxiliary driver that is substantially proportional to said main driver, said equalization mechanism adapted to receive said plurality of binary input signals and generate a set of at least three equalization signals based on said plurality of binary input signals;
- wherein said equalization mechanism includes an element adapted to delay said input signals by a time substantially equal to a bit period.
1 more element
A communication system comprising:
- a first main driver adapted to receive a first plurality of input signals and to output on a first line a first signal that varies over time between N output levels based on said first plurality of input signals, and a second main driver adapted to receive a second plurality of input signals and to output on a second line a second signal that varies over time between N output levels based on said second plurality of input signals, said main drivers adapted to shift from a first of said signal levels to a second of said signal levels by a transition having N−1 possible values for each said first signal level, said transition being substantially equal to a multiple of a difference between adjacent signal levels, said signal levels representing a set of logical states;
- and
- an equalization mechanism including a first auxiliary driver having a gain that is substantially proportional to and smaller than said first main driver, said equalization mechanism configured to receive said first plurality of input signals and to output on said second line a third signal, whereby said third signal compensates for crosstalk on said second line generated by said first signal.
Dependencies are inferred from the claim text.