Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM)
AssigneeInfineon Technologies AG
InventorSiva Raghuram
Life of this patent
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Abstract
The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a printer circuit board (PCB), wherein each DRAM memory chip comprises a predetermined number of stacked DRAM memory dies which are selectable by a memory rank selection signal (r), wherein the memory rank decoder generates the memory rank selection signal (r) in response to external selection signals applied to the dual inline module (DIMM).
Claims11
Dual In Line Memory Module having a predetermined number of memory chips mounted on a printed circuit board wherein each memory chip comprises a predetermined number of stacked memory dies which are selectable by a memory rank selection signal, wherein the memory rank selection signal is generated by a memory rank decoder in response to external selection signals applied to the Dual In Line Memory Module,
- wherein the memory chips are selectable by memory chip select signals, and
- wherein the predetermined number of stacked memory dies is greater than the number of the external selection signals applied to the Dual In Line Memory Module.
Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module having a predetermined number of memory chips mounted on a printed circuit board, wherein each memory chip comprises a predetermined number of stacked memory dies which are selectable by a memory rank selection signal, wherein the memory rank decoder generates the memory rank selection signal in response to external selection signals applied to the dual inline module,
- wherein the memory chips are selectable by memory chip select signals, and
- wherein the predetermined number of stacked memory dies is greater than the number of the external selection signals applied to the Dual In Line Memory Module.
Dependencies are inferred from the claim text.