Oscillator circuit arrangement with an automation feedback control
AssigneeATMEL Germany GmbH
InventorH.-Juergen Schulz
Life of this patent
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Abstract
A circuit arrangement for generating oscillations with a defined frequency includes an oscillator circuit (30, 32) for generating the oscillations and a dedamping circuit (18, 20) connected to the oscillator circuit for compensating any damping of the oscillator circuit. The dedamping or damping compensation by the dedamping circuit is accomplished with the aid of a rectifier circuit (60, 62). The dedamping circuit is a bridge circuit of CMOS field effect transistors (22, 24; 26, 28) which are controlled in their operation in closed loop fashion by respective rectifier circuit branches which are in turn connected to the oscillator circuit to provide a proportional closed loop control of the damping compensation.
Claims19
A circuit arrangement for generating oscillations with a defined frequency, said circuit arrangement comprising an oscillator circuit (30, 32) for generating said oscillations and a dedamping circuit (14, 18, 20) operatively connected to said oscillator circuit (30, 32) for dedamping said oscillator circuit, said dedamping circuit comprising a dedamping bridge circuit of field effect transistors (22, 24, 26, 28) and rectifier circuits (60, 62) operatively connected to said bridge circuit and to said oscillator circuit (30, 32), wherein said dedamping bridge circuit comprises at least one first bridge branch (18), including a first pair of MOSFET transistors (22, 24) complementary to each other and at least one second bridge branch (20) including a second pair of MOSFET transistors (26, 28) complementary to one another, and wherein each of said rectifier circuits comprises a first rectifier circuit branch (60) and a second rectifier circuit branch (62), wherein said first rectifier circuit branch (60) comprises a first terminal and a second terminal connected to a respective control gate (42, 44) of said first pair of MOSFET transistors (22, 24), wherein said second rectifier ranch (62) comprises a third terminal and a fourth terminal connected to a respective control gate (36, 38) of said further pair of MOSFET transistors (26, 28), said oscillator circuit (30, 32) having a first oscillator terminal (34) connected to said first rectifier circuit branch (60), said oscillator circuit (30, 32) having a second oscillator terminal (40) connected to said second rectifier circuit branch (62), whereby said first and second rectifier circuit branches (60, 62) control said control gates in closed loop fashion in response to signals at said first and second oscillator terminals (34, 40), respectively, and wherein each of said first and second rectifier circuit branches (60, 62) comprises a first rectifier diode (74, 86) each with a first anode and a first cathode, and a second rectifier diode (80, 88) each with a second anode and a second cathode, wherein said first rectifier diode and said second rectifier diode of said first and second rectifier circuit branches (60, 62), respectively, are connected in series with each other thereby forming junctions between said first anode and said second cathode of said first and second rectifier circuit branches (60, 62), wherein said junctions are connected to a reference potential, and wherein said first cathode and said second anode are connected to a respective control gate terminal (42, 44;
- 36, 38) of said first and second pair of complementary MOSFET transistors (22, 24;
- 26, 28) forming said dedamping bridge circuit (18, 20).
A circuit arrangement for generating oscillations with a defined frequency, said circuit arrangement comprising an oscillator circuit (30, 32) for generating said oscillations and a dedamping circuit (14, 18, 20) operatively connected to said oscillator circuit (30, 32) for dedamping said oscillator circuit, said dedamping circuit comprising a dedamping bridge circuit of field effect transistors (22, 24, 26, 28) and rectifier circuits (60, 62) operatively connected to said bridge circuit and to said oscillator circuit (30, 32), wherein said dedamping bridge circuit comprises at least one first bridge branch (18), including a first pair of MOSFET transistors (22, 24) complementary to each other and at least one second bridge branch (20) including a second pair of MOSFET transistors (26, 28) complementary to one another, and wherein each of said rectifier circuits comprises a first rectifier circuit branch (60) and a second rectifier circuit branch (62), wherein said first rectifier circuit branch (60) comprises a first terminal and a second terminal connected to a respective control gate (42, 44) of said first pair of MOSFET transistors (22, 24), wherein said second rectifier branch (62) comprises a third terminal and a fourth terminal connected to a respective control gate (36, 38) of said further pair of MOSFET transistors (26, 28), said oscillator circuit (30, 32) having a first oscillator terminal (34) connected to said first rectifier circuit branch (60), said oscillator circuit (30, 32) having a second oscillator terminal (40) connected to said second rectifier circuit branch (62), whereby said first and second rectifier circuit branches (60, 62) control said control gates in closed loop fashion in response to signals at said first and second oscillator terminals (34, 40), respectively, and wherein each of said first and second rectifier circuit branches (60, 62) comprises at least one parallel circuit (66, 68;
- 70, 72) including an ohmic resistor (R) and a capacitor (C) connected in parallel with each other, and wherein each parallel circuit is connected in series with a respective diode (74, 80;
- 86, 88) of said first and second rectifier circuit branches (60, 62).
A circuit arrangement for generating oscillations with a defined frequency, said circuit arrangement comprising an oscillator circuit (30, 32) for generating said oscillations and a dedamping circuit (14, 18, 20) operatively connected to said oscillator circuit (30, 32) for dedamping said oscillator circuit, said dedamping circuit comprising a dedamping full bridge circuit of four field effect transistors (22, 24, 26, 28) and at least four rectifiers (74, 80, 86, 88) operatively connected to said dedamping full bridge circuit and to said oscillator circuit (30, 32), wherein a first pair of rectifiers of said four rectifiers comprises two rectifiers (74, 80) connected in series with each other to form a first series connection connected in parallel to gate terminals (42, 44) of a first pair (22, 24) of said four field effect transistors, wherein a second pair of rectifiers of said four rectifiers comprises two rectifiers (86, 88) also connected in series with each other to form a second series connection connected in parallel to gate terminals (36, 38) of a second pair (26, 28) of said four field effect transistors, said first and second series connections of said first and second pairs of rectifiers having a respective junction (76) connected to a reference potential, wherein said four field effect transistors (22, 24, 26, 28) are interconnected to form first junctions for connection to a power supply (14) and to form second junctions (46, 48) connected to said oscillator circuit (30, 32), wherein said circuit arrangement further comprises four connector circuits (66, 68, 70, 72), and wherein each connector circuit connects a respective transistor gate terminal (36, 38, 42, 44) to said oscillator circuit (30, 32).
Dependencies are inferred from the claim text.