Fully differential operational amplifier with fast settling time

An operational amplifier comprising:

• a first input transistor having a source terminal, a gate terminal and a drain terminal, the gate terminal receiving a first input signal of a pair of differential input signals;
• a second input transistor having a source terminal, a gate terminal and a drain terminal, the source terminal of the second input transistor being connected to the source terminal of the first input transistor, the gate terminal receiving a second input signal of the pair of differential input signals;
• a first cascode transistor having a source terminal, a gate terminal and a drain terminal, the source terminal being connected to the drain terminal of the first input transistor and the drain terminal providing a first output signal of a pair of differential output signals;
• a second cascode transistor having a source terminal, a gate terminal and a drain terminal, the source terminal being connected to the drain terminal of the second input transistor and the drain terminal providing a second output signal of the pair of differential output signals;
• a tail current transistor having a drain terminal connected to the source terminals of the first and second input transistors, a source terminal connected to a ground potential and a gate terminal coupled to a first bias voltage, the tail current transistor conducting a first bias current;
• a first keep-alive transistor having a source terminal being connected to the ground potential, a gate terminal and a drain terminal connected together and to the source terminal of the first cascode transistor, the first keep-alive transistor conducting a second bias current;
• and
• a second keep-alive transistor having a source terminal being connected to the ground potential, a gate terminal and a drain terminal connected together and to the source terminal of the second cascode transistor, the second keep-alive transistor conducting a third bias current,
• wherein the second bias current is a function of a voltage at the source terminal of the first cascode transistor and the third bias current is a function of a voltage at the source terminal of the second cascode transistor, the second bias current and the third bias current each being a variable fraction of the first bias current conducted by the tail current transistor.