Wide-band high-gain limiting amplifier with parallel resistor-transistor source loads

A multi-stage amplifier comprising:

• a transconductance stage receiving a first differential input and a second differential input and driving a first differential intermediate node and a second differential intermediate node;
• a shunt-shunt-feedback stage receiving the first differential intermediate node and the second differential intermediate node as inputs and driving a first differential output and a second differential output;
• wherein the transconductance stage comprises:
• a first differential transistor having a gate receiving the first differential input, a source connected to a first tail node, and a drain driving the first differential intermediate node;
• a first load resistor connected between the first differential intermediate node and a first supply;
• a first load transistor connected between the first differential intermediate node and the first supply and having a gate driven by a first bias voltage;
• wherein the first load resistor and the first load transistor are connected in parallel;
• a first tail transistor having a gate driven by a second bias voltage and a source connected to a second supply and a drain connected to the first tail node;
• a second differential transistor having a gate receiving the second differential input, a source connected to the first tail node, and a drain driving the second differential intermediate node;
• a second load resistor connected between the second differential intermediate node and the first supply;
• a second load transistor connected between the second differential intermediate node and the first supply and having a gate driven by the first bias voltage;
• wherein the second load resistor and the second load transistor are connected in parallel;
• wherein the shunt-shunt-feedback stage comprises:
• a third differential transistor having a gate receiving the first differential intermediate node, a source connected to a second tail node, and a drain driving the first differential output;
• a third load resistor connected between the first differential output and the first supply;
• a third load transistor connected between the first differential output and the first supply and having a gate driven by the first bias voltage;
• wherein the third load resistor and the third load transistor are connected in parallel;
• a fourth differential transistor having a gate receiving the second differential intermediate node, a source connected to the second tail node, and a drain driving the second differential output;
• a fourth load resistor connected between the second differential output and the first supply;
• a fourth load transistor connected between the second differential output and the first supply and having a gate driven by the first bias voltage;
• wherein the fourth load resistor and the fourth load transistor are connected in parallel;
• a second tail transistor having a gate driven by the second bias voltage and a source connected to the second supply and a drain connected to the second tail node;
• a first feedback resistor connected between the first differential intermediate node and the first differential output;
• and
• a second feedback resistor connected between the second differential intermediate node and the second differential output.

An amplifier comprising:

• a first differential input and a second differential input;
• first differential transistor means for controlling a first current between a first intermediate node and a first tail node in response to the first differential input;
• first resistor load means for supplying a current to the first intermediate node from a first supply in response to a voltage difference between the first supply and the first intermediate node;
• first transistor load means for controlling a first load current between the first supply and the first intermediate node in response to a first bias voltage;
• second differential transistor means for controlling a second current between a second intermediate node and the first tail node in response to the second differential input;
• second resistor load means for supplying a current to the second intermediate node from the first supply in response to a voltage difference between the first supply and the second intermediate node;
• second transistor load means for controlling a second load current between the first supply and the second intermediate node in response to the first bias voltage;
• third differential transistor means for controlling a third current between a first differential output and a second tail node in response to the first intermediate node;
• third resistor load means for supplying a current to the first differential output from the first supply in response to a voltage difference between the first supply and the first differential output;
• third transistor load means for controlling a third load current between the first supply and the first differential output in response to the first bias voltage;
• fourth differential transistor means for controlling a fourth current between a second differential output and the second tail node in response to the second intermediate node;
• fourth resistor load means for supplying a current to the second differential output from the first supply in response to a voltage difference between the first supply and the second differential output;
• fourth transistor load means for controlling a fourth load current between the first supply and the second differential output in response to the first bias voltage;
• first feedback means for shunting current between the first differential output and the first intermediate node in response to a voltage difference between the first differential output and the first intermediate node;
• and
• second feedback means for shunting current between the second differential output and the second intermediate node in response to a voltage difference between the second differential output and the second intermediate node.