Processing circuit and method for variable-length coding and decoding
AssigneeEquator Technologies, Inc.
InventorsRichard M. Deeley, Yatin Mundkur, Woobin Lee
Life of this patent
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Abstract
A variable-length encode/decode processor includes a central processing unit and an instruction buffer and a getbits processing engine coupled to the central processing unit. Such a processor can be used to encode data as variable-length symbols or to decode variable-length symbols such as those found in an MPEG bitstream.
Claims26
A variable-length encode/decode processor, comprising:
- a central processing unit;
- a special-purpose processing unit coupled to the central processing unit and operable to process image data according to a block-based coding/decoding standard;
- and
- an input/output buffer coupled to the special-purpose processing unit and operable to transfer the image data between the special-purpose processing unit and an input/output bus;
- wherein the special-purpose processing unit is operable to:
- address a memory location with a value stored in a symbol register;
- retrieve an address from the addressed location;
- and
- store the retrieved address in the symbol register.
A variable-length encode/decode processor, comprising:
- a central processing unit;
- a special-purpose processing unit coupled to the central processing unit and operable to process image data according to a block-based coding/decoding standard;
- an input/output buffer coupled to the special-purpose processing unit and operable to transfer the image data between the special-purpose processing unit and an input/output bus;
- and
- a symbol register coupled to the special-purpose processing unit and to the input/output buffer;
- wherein the special-purpose processing unit is operable to:
- address a memory location with a value stored in the symbol register;
- retrieve an address from the addressed location;
- store the retrieved address in the symbol register.
A variable-length encode/decode processor, comprising:
- a central processing unit;
- a special-purpose processing unit coupled to the central processing unit and operable to process image data according to a block-based coding/decoding standard;
- at least one shared register coupled to the central processing unit and to the special-purpose processing unit;
- at least one memory unit coupled to the central processing unit and to the special-purpose processing unit and operable to store an image;
- and
- a symbol register coupled to the special-purpose processing unit, the shared register, and the memory unit;
- wherein the special-purpose processing unit is operable to:
- form a first address from respective values stored in the symbol register and in the shared register;
- retrieve a value from a location of the memory unit, the location having the first address;
- and
- store the retrieved value in the symbol register.
A variable-length encode/decode processor comprising:
- a central processing unit;
- a special-purpose processing unit coupled to the central processing unit and operable to process image data according to a block-based coding/decoding standard;
- at least one shared register coupled to the central processing unit and to the special-purpose processing unit;
- at least one memory unit coupled to the central processing unit and to the special-purpose processing unit and operable to store an image;
- and
- a symbol register coupled to the special-purpose processing unit, the shared register, and the memory unit;
- wherein the special-purpose processing unit includes a general-purpose register and is operable to:
- form a first address from respective values stored in the symbol register and in the general-purpose register;
- retrieve a value from a location of the memory unit, the location having the first address;
- and
- store the retrieved value in the symbol register.
A variable-length encode/decode processor, comprising:
- a central processing unit;
- a special-purpose processing unit coupled to the central processing unit and operable to process image data according to a block-based coding/decoding standard;
- at least one shared register coupled to the central processing unit and to the special-purpose processing unit;
- at least one memory unit coupled to the central processing unit and to the special-purpose processing unit and operable to store an image;
- and
- a symbol register coupled to the special-purpose processing unit, the shared register, and the memory unit;
- wherein the special-purpose processing unit includes a general-purpose register and is operable to:
- form a first address from respective values stored in the symbol register and in the general-purpose register;
- retrieve a second address from a location of the memory unit having the first address, the second address corresponding to another location of the memory unit that stores a portion of an image;
- and
- store the second address in the symbol register.
A method for image processing, comprising:
- receiving a first stream of data that represents a first version of an image:
- processing the first stream of data with a special-purpose processor under the control of a central processing unit;
- returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit;
- and
- generating a second stream of data that represents a second version of the image;
- wherein returning the state of the special-purpose processor comprises storing in the shared register an address that points to the state.
A method for image processing, comprising:
- receiving a first stream of data that represents a first version of an image;
- processing the first stream of data with a special-purpose processor under the control of a central processing unit;
- returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit;
- and
- generating a second stream of data that represents a second version of the image;
- wherein processing the first data stream comprises processing the first data stream with an arithmetic logic unit in the special-purpose processor;
- and
- returning the state of the special-purpose processor comprises storing a result generated by the arithmetic logic unit in the shared register.
A method for image processing, comprising:
- receiving a first stream of data that represents a first version of an image;
- processing the first stream of data with a special-purpose processor under the control of a central processing unit;
- returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit;
- and
- generating a second stream of data that represents a second version of the image;
- wherein returning the state of the special-purpose processor comprises storing a testable machine state of the special-purpose processor in the shared register.
A method for image processing, comprising:
- receiving a first stream of data that represents a first version of an image;
- processing the first stream of data with a special-purpose processor under the control of a central processing unit;
- returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit;
- and
- generating a second stream of data that represents a second version of the image;
- wherein:
- processing the first data stream comprises adding one to bits eleven to fifteen of a load value stored in a memory to generate a sum;
- and
- returning the state of the special-purpose processor comprises storing the sum in the shared register.
A method for image processing, comprising:
- receiving a first stream of data that represents a first version of an image;
- processing the first stream of data with a special-purpose processor under the control of a central processing unit;
- returning a state of the spccial-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit;
- and
- generating a second stream of data that represents a second version of the image;
- wherein returning the state of the special-purpose processor comprises storing the first sixteen bits of the first data stream in the shared register.
A method for image processing, comprising:
- receiving a first stream of data that represents a first version of an image;
- processing the first stream of data with a special-purpose processor under the control of a central processing unit;
- returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit;
- and
- generating a second stream of data that represents a second version of the image;
- wherein returning the state of the special-purpose processor comprises storing in the first shared register a count of the leading zeros or leading ones in a second register that is shared by the special-purpose processor and the central processing unit.
A method for image processing, comprising:
- receiving a first stream of data that represents a first version of an image;
- processing the first stream of data with a special-purpose processor under the control of a central processing unit;
- returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit;
- and
- generating a second stream of data that represents a second version of the image;
- wherein processing with a special-purpose processor comprises processing the first data stream with a get-bits processing unit.
A method for image processing, comprising:
- receiving a first stream of data that represents a first version of an image;
- processing the first stream of data with a special-purpose processor under the control of a central processing unit;
- returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit;
- and
- generating a second stream of data that represents a second version of the image;
- wherein returning a state further comprises:
- forming a first address from respective values stored in a symbol register and in the first register;
- retrieving the state from a location of memory, the location having the first address;
- and
- storing the retrieved state in the symbol register.
A method for image pfpcessing, comprising:
- receiving a first stream of data that represents a first version of an image;
- processing the first stream of data with a special-purpose processor under the control of a central processing unit;
- returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processin unit;
- and
- generating a second stream of data that represents a second version of the image;
- wherein returning a state further comprises:
- forming a first address from respective values stored in a symbol register and in a general-purpose register in the special-purpose processor;
- retrieving the state from a location of memory, the location having the first address;
- and
- storing the retrieved state in the symbol register.
A method for image processing, comprising:
- receiving a first stream of data that represents a first version of an image;
- processing the first stream of data with a special-purpose processor under the control of a central processing unit;
- returning a state of the special-purpose processor to the central processing unit via a first register shared by the special-purpose processor and the central processing unit;
- and
- generating a second stream of data that represents a second version of the image;
- wherein returning a state further comprises:
- forming a first address from respective values stored in a symbol register and in a general-purpose register in the special-purpose processor;
- and
- storing the first address in the symbol register.
Dependencies are inferred from the claim text.