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US 7,259,428 B2Granted
Semiconductor device using SOI structure having a triple-well region
AssigneeKabushiki Kaisha Toshiba
InventorSatoshi Inaba
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a support substrate, a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm, a silicon layer provided on the buried insulation film, a MOSFET provided in the silicon layer, and a triple-well region provided in the support substrate under the MOSFET.
Claims17
A semiconductor device, comprising:
- a support substrate;
- a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm;
- a silicon layer provided on the buried insulation film;
- a MOSFET provided in the silicon layer, having a channel region;
- a triple-well region comprised of a first well region provided in the support substrate and a second well region formed in the first well region, the second well region overlapping an entire region of the channel region;
- another silicon layer provided on the buried insulation film;
- another MOSFET provided in said another silicon layer;
- and
- another triple-well region that is provided in the support substrate under said another MOSFET.
6 more elements
A semiconductor device, comprising:
- a support substrate;
- a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm;
- a silicon layer provided on the buried insulation film;
- a MOSFET provided in the silicon layer, having a channel region;
- a triple-well region comprised of a first well region provided in the support substrate and a second well region formed in the first well region, the second well region overlapping an entire region of the channel region;
- another silicon layer provided on the buried insulation film;
- and
- another MOSFET provided in said another silicon layer,
- wherein the MOSFET is an n-channel MOSFET, and
- wherein a region, which is doped with an impurity of the same conductivity type as the impurity for forming source/drain regions, is present in a p-well region formed immediately below a channel within the support substrate under the n-MOSFET region.
7 more elements
A semiconductor device, comprising:
- a support substrate;
- a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm;
- a silicon layer provided on the buried insulation film;
- a MOSFET provided in the silicon layer, having a channel region;
- a triple-well region comprised of a first well region provided in the support substrate and a second well region formed in the first well region, the second well region overlapping an entire region of the channel region;
- another silicon layer provided on the buried insulation film;
- and
- another MOSFET provided in said another silicon layer,
- wherein said another silicon layer is insulation-isolated from the silicon layer by an insulating isolation film provided in the support substrate.
6 more elements
A semiconductor device comprising:
- a support substrate;
- a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm;
- a first silicon layer provided on the buried insulation film;
- a second silicon layer provided on the support substrate as a bulk layer;
- a first MOSFET provided in the first silicon layer;
- a second MOSFET provided in the second silicon layer;
- and
- a triple-well region provided in the support substrate under at least each of the first and second MOSFETs.
5 more elements
A semiconductor device comprising:
- a support substrate;
- a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm;
- first and second silicon layers provided on the buried insulation film;
- an insulating isolation layer that is provided in the support substrate and insulation-isolates the first and second silicon layers;
- a fully depleted first MOSFET provided in the first silicon layer;
- a partially depleted second MOSFET provided in the second silicon layer;
- and
- a triple-well region provided in the support substrate under at least each of the first and second MOSFETs.
5 more elements
Dependencies are inferred from the claim text.