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US 7,257,808 B2Granted
System and method to reduce the size of source code in a processing system
AssigneeIntel Corporation
InventorArch D. Robison
Life of this patent
Estimating the term…
Abstract
A system and method to reduce the size of source code in a processing system are described. Multiple subgraph structures are identified within a graph structure constructed for multiple source code instructions in a program. Unifiable variables that are not simultaneously used in the source code instructions are identified within each subgraph structure. Finally, one or more unifiable instructions from a tine of a corresponding subgraph structure are transferred to a handle of the corresponding subgraph structure, each unifiable instruction containing one or more unifiable variables.
Claims28
A method comprising:
- identifying a plurality of fork subgraph structures within a graph structure constructed for a plurality of source code instructions;
- identifying, prior to register allocation, a plurality of unifiable variables within each fork subgraph structure of said plurality of fork subgraph structures, which are not simultaneously used in said plurality of source code instructions;
- constructing a dependence graph of said plurality of source code instructions;
- using said dependence graph to identify at least two unifiable instructions of said plurality of source code instructions, within said plurality of fork subgraph structures, said at least two unifiable instructions containing at least one unifiable variable of said plurality of unifiable variables;
- unifying each unifiable variable within said at least two unifiable instructions to generate a corresponding unified instruction for each of the at least two unifiable instructions;
- and
- transferring said at least two unifiable instructions of said plurality of source code instructions from respective tines of corresponding fork subgraph structures of said plurality of fork subgraph structures to store a matching unified instruction within a handle corresponding to said fork subgraph structures, if the corresponding unified instructions of said at least two unifiable instructions match.
4 more elements
A system comprising:
- means for identifying a plurality of fork subgraph structures within a graph structure constructed for a plurality of source code instructions;
- means for identifying, prior to register allocation, a plurality of unifiable variables within each fork subgraph structure of said plurality of fork subgraph structures, which are not simultaneously used in said plurality of source code instructions;
- means for constructing a dependence graph of said plurality of source code instructions;
- means for using said dependence graph to identify at least one unifiable instruction of said plurality of source code instructions, within said plurality of fork subgraph structures, said at least two unifiable instructions containing at least one unifiable variable of said plurality of unifiable variables;
- means for unifying each unifiable variable within said at least two unifiable instructions to generate a corresponding unified instruction for each of the at least two unifiable instructions;
- and
- means for transferring said at least two unifiable instructions of said plurality of source code instructions from corresponding tines of corresponding fork subgraph structures of said plurality of fork subgraph structures to store a matching unified instruction within a handle corresponding to said fork subgraph structures, if the corresponding unified instructions of said at least two unifiable instructions match.
4 more elements
A computer readable medium containing instructions, which, when executed in a processing system, cause said processing system to perform a method comprising:
- identifying, prior to register allocation, a plurality of fork subgraph structures within a graph structure constructed for a plurality of source code instructions;
- identifying a plurality of unifiable variables within each fork subgraph structure of said plurality of fork subgraph structures, which are not simultaneously used in said plurality of source code instructions;
- constructing a dependence graph of said plurality of source code instructions;
- using said dependence graph to identify at least two unifiable instructions of said plurality of source code instructions, within said plurality of fork subgraph structures, said at least one unifiable instruction containing at least one unifiable variable of said plurality of unifiable variables;
- unifying each unifiable variable within said at least two unifiable instructions to generate a corresponding unified instruction for each of the at least two unifiable instructions;
- and
- transferring said at least two unifiable instructions of said plurality of source code instructions from respective tines of a corresponding fork subgraph structures of said plurality of fork subgraph structures to store the unified instruction within a handle corresponding to said fork subgraph structures, if the corresponding unified instructions of said at least two unifiable instructions match.
4 more elements
A system comprising:
- a memory having stored thereon a plurality of source code instructions to be executed in a program;
- and
- a processor coupled to said memory
- to identify a plurality of fork subgraph structures within a graph structure constructed for said plurality of source code instructions;
- to identify, prior to register allocation, a plurality of unifiable variables within each fork subgraph structure of said plurality of fork subgraph structures, which are not simultaneously used in said plurality of source code instructions;
- to construct a dependence graph of said plurality of source code instructions;
- to use said dependence graph to identify at least one unifiable instruction of said plurality of source code instructions, within said plurality of fork subgraph structures said at least one unifiable instruction containing at least one unifiable variable of said plurality of unifiable variables;
- to unify each unifiable variable within said at least two unifiable instructions to generate a unified instruction for each of the at least two unifiable instructions;
- and
- to transfer said at least two unifiable instructions of said plurality of source code instructions from respective tines of a corresponding fork subgraph structures of said plurality of fork subgraph structures to store a matching unified instruction within a handle corresponding to said fork subgraph structures, if the corresponding unified instructions of said at least two unifiable instructions match.
7 more elements
Dependencies are inferred from the claim text.