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AssigneeMentor Graphics Corporation
InventorsJyotirmoy Daw, Sanjay Gupta, Suresh Krishnamurthy
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A system and method is presented for synthesizing both a design under test (DUT) and its test environment (i.e., the testbench for the DUT), into an equivalent structural model suitable for execution on a reconfigurable hardware platform. This may be achieved without any change in the existing verification methodology. Behavioral HDL may be translated into a form that can be executed on a reconfigurable hardware platform. A set of compilation transforms are provided that convert behavioral constructs into RTL constructs that can be directly mapped onto an emulator. Such transforms are provided by introducing the concepts of a behavioral clock and a time advance finite state machine (FSM) that determines simulation time and sequences concurrent computing blocks in the DUT and the testbench.
A method for verifying a circuit design by mapping a circuit design and an associated testbench onto a reconfigurable hardware platform, said method comprising the steps of:
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