Method and system for designing a timing closure of an integrated circuit

A method for minimizing interconnect delay in an integrated circuit, the method comprising the steps of:

• a. instantiating a first repeater between at least one block and a corresponding blockage of an integrated circuit if an interconnect crosses a blockage, the instantiation of the first repeater being based on pre-determined criteria;
• and
• b. instantiating one or more second repeaters between at least one pair of connected blocks depending upon a corresponding interconnect drive, the instantiation of the one or more second repeaters being based on the pre-determined criteria;
• determining a size of the one or more second repeaters and the first repeater based on a buffer rule file.

The method for minimizing interconnect delay in an integrated circuit, the method comprising the steps of:

• a. instantiating a first repeater between at least one block and a corresponding blockage of an integrated circuit if an interconnect crosses a blockage, the instantiation of the first repeater being based on pre-determined criteria:
• b. instantiating one or more second repeaters between at least one pair of connected blocks depending upon a corresponding interconnect drive, the instantiation of the one or more second repeaters being based on the pre-determined criteria:
• and
• c. determining whether the integrated circuit is distance-driven the integrated circuit is capacitance-driven, or the integrated circuit is distance and capacitance driven;
• if the integrated circuit is distance-driven, then
• i. selecting a smallest repeater with maximum capacitance corresponding to a distance drive need of the interconnect, the selection being made from a buffer rule file;
• else
• ii. selecting the smallest repeater with maximum distance corresponding to a capacitance need of the interconnect, the selection being made from the buffer rule file.

A computer program product for use with a computer, the computer program product comprising a computer usable medium having a computer readable program code embodied therein for designing a timing closure of an integrated circuit, the computer program code performing;

• a. instantiating a minimum repeater between at least one block and a corresponding blockage of an integrated circuit if an interconnect crosses the blockage and according to a drive of the blockage, the instantiation of the minimum repeater being based on a buffer rule file;
• and
• b. instantiating one or more smallest repeaters between at least one pair of connected blocks depending upon a corresponding interconnect, the instantiation of the smallest repeater being based on pre-determined criteria;
• determining a size of the one or more smallest repeaters based on the buffer rule file.