Method of automatic shape-based routing of interconnects in spines for integrated circuit design

A method of routing at least two interconnects of an integrated circuit comprising:

• identifying a first set of at least two pins to couple;
• calculating a route area, the route area extending a distance in a first direction to comprise positions in the first direction of the at least two pins;
• routing a first spine interconnect extending in the first direction at least a length from a first pin to a second pin in the first direction;
• determining a position in a second direction, orthogonal to the first direction, for the first spine interconnect to reduce an average length of the plurality of stitching interconnects;
• routing a plurality of stitching interconnects in the second direction to couple the first pin and second pin to the first spine interconnect, wherein a position in the second direction of the first spine interconnect is based on a weighted average of positions in the second direction of the first set of at least two pins;
• identifying a second set of at least two pins to couple wherein the second set comprises at least a third pin and a fourth pin;
• in the route area, routing a second spine interconnect extending in the first direction at least a length from the third pin to the fourth pin the first direction;
• determining a position in a second direction, orthogonal to the first direction, for the second spine interconnect to reduce an average length of the plurality of stitching interconnects;
• routing a plurality of stitching interconnects in the second direction to couple the third pin and fourth pin to the second spine interconnect, wherein a position in the second direction of the second spine interconnect is based on a weighted average of positions in the second direction of the second set of at least two pins;
• placing a first shield on a first side of the first spine interconnect;
• and
• placing a second shield interconnect adjacent to the second spine interconnect, wherein the first and second spine interconnects are between the first and second shield interconnects.

A method of routing at least one interconnect of an integrated circuit comprising:

• identifying at least two pins to couple, wherein each pin has a position in a first direction and a position in a second direction, orthogonal to the first direction;
• calculating a route area, the route area extending a distance in the first direction to comprise positions in the first direction of the at least two pins;
• determining if at least one forbidden area is located within the route area, wherein the at least one forbidden area extends in the first direction the entire length of the route area in the first direction and comprises at least one obstacle;
• routing a spine interconnect extending in the first direction at least a length from a first pin to a second pin in the first direction, wherein the routing the spine interconnect excludes the at least one forbidden area;
• and
• routing a plurality of stitching interconnects in the second direction to couple the first pin and second pin to the spine interconnect,
• wherein a position in the second direction of the spine interconnect is at an available position, outside the at least one forbidden area, closest to a position based on a weighted average of positions in the second direction of the at least two pins.

A method of routing at least two interconnects of an integrated circuit comprising:

• identifying N pins to couple;
• calculating a rectangular route area comprising the positions in a first direction of the N pins;
• determining if at least one forbidden area is located within the route area, wherein the at least one forbidden area is a rectangular area comprising at least one obstacle and extends an entire length of the route area in the first direction;
• routing, outside of the forbidden area, a first spine interconnect extending in the first direction an entire length of the route area in the first direction;
• determining a position in a second direction, orthogonal to the first direction, for the spine interconnect to reduce an average length of N stitching interconnects;
• routing N stitching interconnects in the second direction to couple each of the N pins to the spine interconnect, wherein the position in the second direction of the spine interconnect is based on a quotient of a sum of the positions of the N pins in the second direction and N;
• identifying M pins to couple;
• routing, outside of the forbidden area, a second spine interconnect extending in the first direction an entire length of the route area in the first direction;
• determining a position in the second direction for the second spine interconnect to reduce an average length of M stitching interconnects;
• routing M stitching interconnects in the second direction to couple each of the M pins to the second spine interconnect, wherein the position in the second direction of the second spine interconnect is based on a quotient of a sum of the positions of the M pins in the second direction and M;
• placing a first shield on a first side of the first spine interconnect;
• and
• placing a second shield interconnect adjacent to the first spine interconnect, between the first spine interconnect and the second spine interconnect.

A method of routing at least one interconnect of an integrated circuit comprising:

• identifying N pins to couple, wherein each pin has a position in a first direction and a position in a second direction, orthogonal to the first direction;
• calculating a rectangular route area comprising the positions in the first direction of the N pins;
• determining if at least one forbidden area is located within the route area, wherein the at least one forbidden area is a rectangular area comprising at least one obstacle and extends an entire length of the route area in the first direction;
• routing, outside of the forbidden area, a spine interconnect extending in the first direction an entire length of the route area in the first direction;
• determining a position in the second direction, orthogonal to the first direction, for the spine interconnect to reduce an average length of N stitching interconnects;
• and
• routing N stitching interconnects in the second direction to couple each of the N pins to the spine interconnect, wherein the position in the second direction of the spine interconnect is at a position, outside the forbidden area, closest to a position based on a weighted average of positions in the second direction of the N pins.

A method of routing a plurality of nets of an integrated circuit comprising:

• identifying pins to couple for each net;
• calculating a route area for each net, wherein each route area comprises positions in a first direction of the pins for a net;
• determining for each route area if at least one forbidden area is located within the route area, wherein a forbidden area includes at least one obstacle and extends in the first direction an entire length of the corresponding route area in the first direction;
• routing, outside of the at least one forbidden area, a plurality of spine interconnects extending in a first direction the entire length of each corresponding route area in the first direction;
• routing a plurality of stitching interconnects in a second direction to couple each of the pins to the corresponding spine interconnect;
• automatically routing a first interconnect to match a timing delay of a second interconnect by lengthening the first interconnect;
• placing a first shield on a first side of at least one spine interconnect;
• and
• placing a second shield on a second side of the at least one spine interconnect.

A method of routing a plurality of nets of an integrated circuit comprising:

• identifying pins to couple for each net;
• calculating a route area for each net, wherein each route area comprises positions in a first direction of the pins for a net.
• determining for each route area if at least one forbidden area is located within the route area, wherein a forbidden area includes at least one obstacle and extends in the first direction an entire length of the corresponding route area in the first direction;
• routing, outside of the at least one forbidden area, a plurality of spine interconnects extending in a first direction the entire length of each corresponding route area in the first direction;
• routing a plurality of stitching interconnects in a second direction to couple each of the pins to the corresponding spine interconnect;
• automatically routing a first interconnect to match a timing delay of a second interconnect by increasing a spacing between the first interconnect and a third interconnect;
• placing a first shield on a first side of at least one spine interconnect;
• and
• placing a second shield on a second side of the at least one spine interconnect.

A computer program product stored on a computer-readable storage medium for routing at least two interconnects of an integrated circuit comprising:

• code for identifying a first and a second set of at least two pins to couple;
• code for calculating a route area, the route area extending a distance in a first direction to include positions in the first direction of the first set of at least two pins;
• code for routing a first spine interconnect extending in the first direction an entire length of the route area in the first direction;
• code for determining a position in a second direction, orthogonal to the first direction, for the first spine interconnect to reduce an average length of the plurality of stitching interconnects;
• code for routing a plurality of stitching interconnects in a second direction to couple each of the first set of at least two pins to the first spine interconnect, wherein the second direction is orthogonal to the first direction and a position in the second direction of the spine interconnect is based on a weighted average of positions in the second direction of the first set of at least two pins;
• code for routing a second spine interconnect extending in the first direction an entire length of the route area in the first direction;
• code for determining a position in the second direction for the second spine interconnect to reduce an average length of the plurality of stitching interconnects;
• code for routing a plurality of stitching interconnects in the second direction to couple each of the second set of at least two pins to the second spine interconnect, wherein a position in the second direction of the spine interconnect is based on a weighted average of positions in the second direction of the second set of at least two pins;
• code for placing a first shield interconnect adjacent to the first spine interconnect on a first side;
• and
• code for placing a second shield interconnect adjacent to the first spine interconnect, between the first spine interconnect and the second spine interconnect.

A method comprising:

• providing N pins to couple together using a net;
• finding a rectangular route region comprising the N pins, having a length greater than a width, wherein the length is in a first direction and the width is a second direction, orthogonal to the first direction;
• in the rectangular route region, placing a first spine interconnect extending in the first direction at a position in the second direction based on a weighted average of positions of the N pins;
• routing N stitching interconnects in the second direction to couple each of the N pins to the first spine interconnect, wherein the first spine interconnect and N stitching interconnects forms a first interconnect track;
• providing M pins to couple together using a net;
• in the rectangular route region, placing a second spine interconnect extending in the first direction at a position in the second direction based on a weighted average of positions of the M pins;
• routing M stitching interconnects in the second direction to couple each of the M pins to the second spine interconnect, wherein the second spine interconnect and M stitching interconnects forms a second interconnect track;
• placing a first shield interconnect adjacent to the first spine interconnect, on a first side;
• and
• placing a second shield interconnect adjacent to the first spine interconnect, between the first spine interconnect and the second spine interconnect.

A method comprising:

• providing N pins to couple together using a net;
• finding a rectangular route region comprising the N pins, having a length greater than a width, wherein the length is in a first direction and the width is a second direction, orthogonal to the first direction;
• in the rectangular route region, placing a first spine interconnect extending in the first direction at a position in the second direction based on a weighted average of positions of the N pins;
• routing N stitching interconnects in the second direction to couple each of the N pins to the first spine interconnect, wherein the first spine interconnect and N stitching interconnects forms a first interconnect track;
• providing M pins to couple together using a net;
• in the rectangular route region, placing a second spine interconnect extending in the first direction at a position in the second direction based on a weighted average of positions of the M pins;
• routing M stitching interconnects in the second direction to couple each of the M pins to the second spine interconnect, wherein the second spine interconnect and M stitching interconnects forms a second interconnect track;
• placing a first shield interconnect adjacent to the first spine interconnect on a first side;
• and
• placing a second shield interconnect adjacent to the second spine interconnect, wherein the first and second spine interconnects are between the first and second shield interconnects.

A method comprising:

• providing N pins to couple together using a net;
• finding a rectangular route region, comprising the N pins, having a length greater than a width, wherein the length is in a first direction and the width is a second direction, orthogonal to the first direction;
• in the rectangular route region, placing a first spine interconnect extending in the first direction at a position in the second direction based on a quotient of a sum of the positions of the N pins in the second direction and N;
• routing N stitching interconnects in the second direction to couple each of the N pins to the first spine interconnect, wherein the first spine interconnect and N stitching interconnects forms a first interconnect track;
• providing M pins to couple together using a net;
• in the rectangular route region, placing a second spine interconnect extending in the first direction at a position in the second direction based on a weighted average of positions of the M pins;
• routing M stitching interconnects in the second direction to couple each of the M pins to the second spine interconnect, wherein the second spine interconnect and M stitching interconnects forms a second interconnect track;
• placing a first shield interconnect adjacent to the first spine interconnect on a first side;
• and
• placing a second shield interconnect adjacent to the first spine interconnect, between the first spine interconnect and the second spine interconnect.

A method comprising:

• providing N pins to couple together using a net;
• finding a rectangular route region comprising the N pins, having a length greater than a width, wherein the length is in a first direction and the width is a second direction, orthogonal to the first direction;
• in the rectangular route region, placing a first spine interconnect extending in the first direction at a position in the second direction based on a quotient of a sum of the positions of the N pins in the second direction and N;
• routing N stitching interconnects in the second direction to couple each of the N pins to the first spine interconnect, wherein the first spine interconnect and N stitching interconnects forms a first interconnect track;
• providing M pins to couple together using a net;
• in the rectangular route region, placing a second spine interconnect extending in the first direction at a position in the second direction based on a weighted average of positions of the M pins;
• routing M stitching interconnects in the second direction to couple each of the M pins to the second spine interconnect, wherein the second spine interconnect and M stitching interconnects forms a second interconnect track;
• placing a first shield interconnect adjacent to the first spine interconnect on a first side;
• and
• placing a second shield interconnect adjacent to the second spine interconnect, wherein the first and second spine interconnects are between the first and second shield interconnects.

A computer program product stored on a computer-readable storage medium for routing at least two interconnects of an integrated circuit comprising:

• code for identifying a first and a second set of at least two pins to couple;
• code for calculating a route area, the route area extending a distance in a first direction to include positions in the first direction of the first set of at least two pins;
• code for routing a first spine interconnect extending in the first direction an entire length of the route area in the first direction;
• code for determining a position in a second direction, orthogonal to the first direction, for the first spine interconnect to reduce an average length of the plurality of stitching interconnects;
• code for routing a plurality of stitching interconnects in a second direction to couple each of the first set of at least two pins to the first spine interconnect, wherein the second direction is orthogonal to the first direction and a position in the second direction of the spine interconnect is based on a weighted average of positions in the second direction of the first set of at least two pins;
• code for routing a second spine interconnect extending in the first direction an entire length of the route area in the first direction;
• code for determining a position in the second direction for the second spine interconnect to reduce an average length of the plurality of stitching interconnects;
• code for routing a plurality of stitching interconnects in the second direction to couple each of the second set of at least two pins to the second spine interconnect, wherein a position in the second direction of the spine interconnect is based on a weighted average of positions in the second direction of the second set of at least two pins;
• code for placing a first shield interconnect adjacent to the first spine interconnect on a first side;
• and
• code for placing a second shield adjacent to the second spine interconnect, wherein the first spine interconnect and the second spine interconnect are between the first shield and the second shield.

A method of routing at least two interconnects of an integrated circuit comprising:

• identifying N pins to couple;
• calculating a rectangular route area comprising the positions in a first direction of the N pins;
• determining if at least one forbidden area is located within the route area, wherein the at least one forbidden area is a rectangular area comprising at least one obstacle and extends an entire length of the route area in the first direction;
• routing, outside of the forbidden area, a first spine interconnect extending in the first direction an entire length of the route area in the first direction;
• determining a position in a second direction, orthogonal to the first direction, for the spine interconnect to reduce an average length of N stitching interconnects;
• routing N stitching interconnects in the second direction to couple each of the N pins to the spine interconnect, wherein the position in the second direction of the spine interconnect is based on a quotient of a sum of the positions of the N pins in the second direction and N;
• identifying M pins to couple;
• routing, outside of the forbidden area, a second spine interconnect extending in the first direction an entire length of the route area in the first direction;
• determining a position in the second direction for the second spine interconnect to reduce an average length of M stitching interconnects;
• routing M stitching interconnects in the second direction to couple each of the M pins to the second spine interconnect, wherein the position in the second direction of the second spine interconnect is based on a quotient of a sum of the positions of the M pins in the second direction and M;
• placing a first shield on a first side of the first spine interconnect;
• and
• placing a second shield interconnect adjacent to the second spine interconnect, wherein the first and second spine interconnects are between the first and second shield interconnects.