Multiple buffer insertion in global routing

A process of creating a table of optimal buffer types useful for designing integrated circuit chips containing buffers, comprising:

• a) creating an array having dimensions including height, input capacitance, output capacitance and ramptime;
• b) identifying a plurality of intervals of buffer output capacitance ranges for buffers having a selected height and selected input pin capacitance,
• c) identifying each buffer in each output capacitance interval having the selected height and input pin capacitance,
• d) defining a plurality of buffer ramptime intervals of a range of buffer ramptimes represented by the buffers identified in step c,
• e) for each buffer ramptime interval identified in step d identifying an optimal buffer type based on the buffers identified in step c and inserting the optimal buffer type into the table at a position along the dimensions that is representative of the selected height, the selected input capacitance, the respective output capacitance interval and the respective ramptime interval, and
• f) repeating steps b-e for all buffer heights and all input pin capacitances for each buffer output capacitance interval.

A computer useable medium having a computer readable program embodied therein for controlling a computer containing a computer-readable file that defines an integrated circuit chip having an initial circuit performance based on initial circuit parameters, the computer further containing a computer-readable table identifying buffer types based on a plurality of circuit parameters, the computer readable program operating the computer to insert one or more buffers into the computer-readable file, the computer readable program comprising:

• computer readable program code, which accesses the table along a plurality of dimensions including height, input capacitance, output capacitance and ramptime;
• first computer readable program code for causing the computer to define a routing tree comprising root, internal and leaf vertices arranged so that each internal and leaf vertex has one parent vertex and each root and internal vertex has at least one child vertex, the parent and child vertices defining respective tree segments, and each internal vertex has an associated set of initial circuit parameters of the chip;
• second computer readable program code for causing the computer to compare the initial circuit parameters associated with an internal vertex to the circuit parameters associated with buffers identified in the table to identify whether to insert a buffer identified in the table inserted to the respective internal vertex;
• and
• third computer readable program code for causing the computer to insert an optimal buffer identified in the table to a segment associated with a selected internal vertex based at least in part on the comparison results.