LSI design method

An LSI design method, comprising:

• estimating a timing uncertainty in an early design stage for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing;
• and
• defining a timing margin value in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with design in respective design stages accordingly,
• wherein in estimating the timing uncertainty relating to an influence of on-chip variation as one of said respective items requiring consideration,
• a judgment is given as to whether or not a clock tree structure is estimable, and if not, the timing uncertainty is estimated corresponding to an operating frequency;
• and
• if estimable the timing uncertainty is estimated corresponding to an on-chip variation factor and a delay time in a path between a clock path branching point and a cell being subjected to a timing check.

An LSI design method, comprising:

• estimating a timing uncertainty in an early design stage for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing;
• and
• defining a timing margin value in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with design in respective design stages accordingly,
• wherein in estimating the timing uncertainty relating to an influence of crosstalk delay as one of said respective items requiring consideration,
• a factor value corresponding to an operating frequency is assumed for calculating an assumed value of the timing uncertainty and a judgment is given as to whether or not a crosstalk delay countermeasure condition is satisfied by the assumed value;
• and
• if satisfied, the timing uncertainty is estimated by defining the factor value corresponding to the assumed value.

An LSI design method, comprising:

• estimating a timing uncertainty in an early design stage for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing;
• and
• defining a timing margin value in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with design in respective design stages accordingly,
• wherein in estimating the timing uncertainty relating to an influence of phased locked loop jitter as one of said respective items requiring consideration,
• the timing uncertainty is estimated corresponding to a characteristic and circuit aspect of the phased locked loop.

An LSI design method, comprising:

• estimating a timing uncertainty in an early design stage for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing;
• and
• defining a timing margin value in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with design in respective design stages accordingly,
• wherein in estimating the timing uncertainty relating to an influence of gap between a temporary and a real wirings as one of said respective items requiring consideration,
• a judgment is given as to whether or not an area estimation is performed, and if not, the timing uncertainty is estimated by setting a factor value corresponding to an operating frequency for calculating the timing uncertainty according to a wire load model;
• while if an area estimation is performed, a judgment is given as to whether or not a wire load model specific to a subject LSI for design is made after the area estimation, and if not, the timing uncertainty is estimated by setting the factor value according to the wire load model and a result of the area estimation;
• and
• if a wire load model specific to a subject LSI for design is made based on a result of the area estimation, the timing uncertainty is estimated by setting the factor value according to the specific wire load model.

A program stored in a computer-readable medium for use in a computer for designing an LSI, for having the computer operate the steps of

• estimating a timing uncertainty in an early design stage for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing;
• and
• defining a timing margin value in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with design in respective design stages accordingly,
• wherein the timing uncertainty is estimated corresponding to each item to be considered for establishing the timing margin value considering a condition of a product specification, an operating condition and a sign-off condition of an LSI prior to a logic synthesis stage;
• and
• the timing uncertainty is estimated in the early design stage relating to an influence of on-chip variation.

A computer readable portable memory media for storing program for use in a computer for designing an LSI, for having the computer operate the steps of

• estimating a timing uncertainty in an early design stage for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing;
• and
• defining a timing margin value in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with design in respective design stages accordingly,
• wherein the timing uncertainty is estimated corresponding to each item to be considered for establishing the timing margin value considering a condition of a product specification, an operating condition and a sign-off condition of an LSI prior to a logic synthesis stage;
• and
• the timing uncertainty is estimated in the early design staae relating to an influence of on-chip variation.