US 7,257,785 B2Granted

Method and apparatus of evaluating layer matching deviation based on CAD information

AssigneeSII NanoTechnology Inc.

InventorRyoichi Matsuoka

Life of this patent

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Abstract

An apparatus of evaluating a layer matching deviation based on CAD information of the invention, is provided with means for storing CAD data and a function of displaying to overlap a scanning microscope image of a pattern of a semiconductor device formed on a wafer and a design CAD image read from the storing means and a function of evaluating acceptability of formation of the pattern by displaying to overlap a pattern image of the semiconductor device formed on the wafer and the design CAD image of the pattern, in addition thereto, a function capable of evaluating acceptability of formation of the pattern also with regard to a shape and positional relationship with a pattern formed at a later step by displaying to overlap a design CAD image of the pattern formed at the later step.

Claims9

Dependent claims

An apparatus for evaluating a deviation between patterns that are successively formed on a wafer to fabricate a semiconductor device, comprising:

a memory for storing CAD data used to form the successively formed patterns of the semiconductor device;
a microscope for obtaining an image of an already formed one of the patterns on the semiconductor wafer;
a monitor for displaying the image obtained with the microscope;
means for reading first CAD data used to form the already formed pattern of the semiconductor device and reading second CAD data to be used to form another pattern of the semiconductor device that will be connected to the already formed pattern;
and
means for displaying the first and second CAD data with the displayed image of the already formed pattern as an overlapped image on the monitor to enable evaluation of a deviation of the already formed pattern from the first and second CAD data.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/823,104Filed 13 Apr 2004 · division
Priority: JP 2001-16075529 May 2001
Published: US 2004/0194042 A130 Sep 2004
Granted: 14 Aug 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G03F 7/70616
Workpiece metrology: monitoring the printed patterns
G03F 7/70633
Monitoring the printed patterns: overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the…
G05B 2219/37205
Measurements: compare measured, vision data with computer model, cad data
G05B 2219/45031
Nc applications: manufacturing semiconductor wafers

Family

Application10/147,417Parent of this division · filed 16 May 2002
US 2004/0194042 A1Pre-grant publication · published 30 Sep 2004
US 6,757,875 B2Parent of this division
US 2002/0184605 A1Published application
US 7,257,785 B2This patent

From the US filing history. Foreign family members aren’t listed.