Method and apparatus for reducing power consumption in an integrated circuit chip
AssigneeSynopsys, Inc.
InventorsPei-Hsin Ho, Yongseok Cheon, Qinke Wang
Life of this patent
Estimating the term…
Abstract
A system that reduces power consumption in an integrated circuit. During operation the system receives a placement for the integrated circuit. The system then groups registers in the placement into clusters and builds a temporary clock tree for the registers within the placement. Next the system assigns net weights to clock wires in the temporary clock tree and signal wires between the rest of the cells of the circuit, and uses the assigned net weights to optimize placement of the cells of the circuit by minimizing a sum of the weighted costs of the wires, wherein the weighted cost of a wire is a product of the net weight of the wire and the length of the wire.
Claims24
A method for reducing power consumption in an integrated circuit, comprising:
- receiving a placement for the integrated circuit;
- grouping registers in the placement into clusters;
- building a temporary clock tree for the registers within the placement;
- assigning net weights to clock wires in the temporary clock tree;
- and
- using the assigned net weights of the clock wires to optimize placement of registers by minimizing a sum of the weighted costs of the clock wires;
- wherein the weighted cost of a clock wire is a product of the net weight of the clock wire and the length of the clock wire;
- and
- wherein the net weight is a sum of a timing-weight component and a power-weight component associated with a net switching power.
An apparatus for reducing power consumption in an integrated circuit, comprising:
- a placer;
- wherein the placer is configured to:
- receive a placement for the integrated circuit;
- group registers in the placement into clusters;
- build a temporary clock tree for the registers within the placement;
- assign net weights to clock wires in the temporary clock tree;
- and
- use the assigned net weights of the clock wires to optimize placement of registers by minimizing a sum of the weighted costs of the clock wires;
- wherein the weighted cost of a clock wire is a product of the net weight of the clock wire and the length of the clock wire;
- and
- wherein the net weight is a sum of a timing-weight component and a power-weight component associated with a net switching power.
A computer system for reducing power consumption in an integrated circuit, comprising:
- a placer;
- wherein the placer is configured to:
- receive a placement for the integrated circuit;
- group registers in the placement into clusters;
- build a temporary clock tree for the registers within the placement;
- assign net weights to clock wires in the temporary clock tree;
- and
- use the assigned net weights of the clock wires to optimize placement of registers by minimizing a sum of the weighted costs of the clock wires;
- wherein the weighted cost of a clock wire is a product of the net weight of the clock wire and the length of the clock wire;
- and
- wherein the net weight is a sum of a timing-weight component and a power-weight component associated with a net switching power.
Dependencies are inferred from the claim text.