Memory interface with write buffer and encoder
AssigneeLSI Corporation
InventorsJeffrey J. Holm, David Parker, Bradley J. Winter
Life of this patent
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Abstract
A method and apparatus are provided for interfacing between a data source and a tightly-coupled memory. In the method and apparatus, a write data word and a write address are received from the data source and latched in a first clock cycle within a write buffer along a write data path, between the data source and the memory. The write data word is encoded according to an error detection code along the write data path. The write address and the write data word are applied to the memory from the write buffer. The write data word is accessible to the data source from the write data path or the memory beginning with a second clock cycle, which is a next subsequent clock cycle to the first clock cycle.
Claims19
A method of interfacing between a data source and a tightly-coupled memory, the method comprising:
- (a) receiving a write data word and a write address from the data source;
- (b) latching the write address and the write data word in a write buffer along a write data path between the data source and the memory;
- (c) encoding the write data word according to an error detection code along the write data path;
- (d) after step (b), applying the write address and the write data word from the write buffer to the memory;
- (e) performing steps (a) and (b) in a first clock cycle;
- and
- (f) making the write data word accessible to the data source from the write data path or the memory beginning with a second clock cycle, which is a next subsequent clock cycle to the first clock cycle.
An integrated circuit data storage and retrieval device comprising:
- a memory;
- a data source for providing write data words, corresponding write addresses and read addresses to the memory;
- a write data path from the data source to the memory, which comprises a write buffer and an error detection encoder, wherein the write buffer latches the write data words and write addresses prior to applying the write data words and write addresses to the memory;
- and
- a read data path from the memory and the write data path to the data source, which provides a read data word from the memory or the write buffer when the data source provides a read address, and wherein the read data word is available to the data source from the read data path within a single clock cycle.
A memory interface circuit comprising:
- a write data input, an address input, a delayed write data output, a delayed write address output, a read data input and a read data output;
- a write buffer coupled between the write data input and the delayed write data output and between the address input and the delayed write address output;
- an error detection encoder coupled in a write data path between the write data input and the delayed write data output;
- an address comparator, which compares the address input with the delayed write address output to produce a comparator result;
- and
- a multiplexer, which couples the read data input or the delayed write data output to the read data output based on the comparator result.
Dependencies are inferred from the claim text.