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US 7,257,757 B2Granted
Flexible accelerators for physical layer processing
AssigneeIntel Corporation
InventorsAnthony L. Chun, Ernest T. Tsui, Walter L. Snyder
Life of this patent
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Abstract
Flexible, micro-coded accelerators are applied to perform physical layer processing in communications applications. The accelerators are reconfigurable and may be programmed to incorporate new protocols as they are introduced.
Claims27
A circuit, comprising:
- a filter processing element reconfigurable to process a signal by use of at least one process selected from a group comprising of digital filtering, adaptive equalization, resampling, despreading, and fast-Fourier transforming;
- at least one decoding processing element to decode and correct errors in said signal;
- a general purpose processing element to process said signal by use of at least one code process selected from a reconfiguration group comprising of deinterleaving, descrambling, cyclic redundancy checking, convolutional encoding, Reed-Solomon encoding, turbo encoding, and Trellis encoding;
- and
- one or more control units to direct the operations of the processing elements according to a first set of protocols,
- wherein the processing elements are coupled in a network.
3 more elements
A method, comprising:
- determining operations of one or more reconfigurable processing elements according to a first set of protocols;
- receiving a signal from a network at a reconfigurable filter processing element;
- processing said signal at said filter processing element by use of at least one process selected from a reconfiguration group comprising of digital filtering, adaptive equalization, resampling, despreading, and fast-Fourier transforming;
- decoding said signal to decode and correct errors in said signal by at least one decoding processing element;
- and
- processing said signal by a general purpose processing element by use of at least one code process selected from a reconfiguration group comprising of deinterleaving, descrambling, cyclic redundancy checking, convolutional encoding, Reed-Solomon encoding, turbo encoding, and Trellis encoding.
3 more elements
A computer-readable medium that provides instructions, which when executed by a processing element, cause the processing element to perform operations comprising micro-coded accelerator based operations of:
- receiving a signal from a network at a reconfigurable filter processing element;
- processing said signal at said filter processing element by use of at least one process selected from a reconfiguration group comprising of digital filtering, adaptive equalization, resampling, despreading, and fast-Fourier transforming;
- decoding said signal to decode and correct errors in said signal by at least one decoding processing element;
- and
- processing said signal by a general purpose processing element by use of at least one code process selected from a reconfiguration group comprising of deinterleaving, descrambling, cyclic redundancy checking, convolutional encoding, Reed-Solomon encoding, turbo encoding, and Trellis encoding.
2 more elements
Dependencies are inferred from the claim text.