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US 7,257,756 B2Granted
Digital frequency synthesis clocked circuits
AssigneeIntel Corporation
InventorsNeal Wolff, Chee How Lim
Life of this patent
Estimating the term…
Abstract
Embodiments of the invention may include a reference input port to receive a reference clock, the reference clock being based on a bypass clock, a feedback input port to receive a feedback clock from a clocked circuit, and logic to compare the reference clock and the feedback clock and to generate an output based on the comparison.
Claims33
An apparatus comprising:
- a bypass clock input to receive a bypass clock from an external source for bypass clock operation;
- a reference input port to receive a reference clock, the reference clock being based alternately on an external oscillator for normal operation or on the bypass clock;
- a clock selection multiplexer to select the bypass clock for bypass operation or the reference clock for normal operation;
- a feedback input port to receive a feedback clock from a clocked circuit;
- and
- logic to compare the reference clock based on the bypass clock in bypass operation and the feedback clock and to generate an output based on the comparison the output being a signal to indicate whether the reference clock and the feedback clock are aligned.
3 more elements
A computer system comprising:
- a voltage controlled crystal oscillator to generate a primary clock;
- a phase locked loop having a first input to receive the primary clock, a second input to receive a feedback clock from a clocked circuit, and an circuit;
- a phase locked loop output to generated a synchronized clock for normal operation;
- a bypass gate to select one of the synchronized clock for normal operation or a bypass clock for bypass operation to apply as a timing signal for the clocked circuit;
- and
- logic to compare a reference clock and the feedback clock and to adjust the timing of the bypass clock independent of the phase locked loop based on the comparison, wherein the reference clock is based on the bypass clock.
3 more elements
A method comprising:
- receiving a bypass clock from an external source for bypass clock operation;
- receiving a reference clock, the reference clock being based alternately on an external oscillator for normal operation or on the bypass clock;
- selecting one of the bypass clock for bypass operation or the reference clock for normal operation;
- receiving a feedback clock from a clocked circuit;
- and
- comparing the reference clock and the feedback clock in bypass operation and generating an output based on the comparison, the output being a signal to indicate whether the reference clock and the feedback clock are aligned.
3 more elements
An article of manufacture comprising a machine-accessible medium including data that, when accessed by a machine, cause the machine to perform operations comprising:
- receiving a bypass clock from an external source for bypass clock operation;
- receiving a reference clock, the reference clock being based alternately on an external oscillator for normal operation or on the bypass clock;
- selecting one of the bypass clock for bypass operation or the reference clock for normal operation;
- receiving a feedback clock from a clocked circuit;
- and
- comparing the reference clock and the feedback clock in bypass operation and generating an output based on the comparison, the output being a signal to indicate whether the reference clock and the feedback clock are aligned.
3 more elements
Dependencies are inferred from the claim text.