Semiconductor testing apparatus
AssigneeAdvantest Corporation
InventorKazuhiko Sato
Life of this patent
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Abstract
A semiconductor testing apparatus capable of reducing time required for testing or repairing a plurality of semiconductor devices. The semiconductor testing apparatus performs test for a plurality of DUT in parallel and performs repair for the plurality of DUT in parallel. For this, the apparatus includes an ALPG, a PDS, an AFM, a driver pin processor, an IO pin processor, a driver channel, and an IO channel. The IO pin processor has a plurality of sub-FC units. When test is performed simultaneously for a plurality of DUT, an individual pattern waveform is generated corresponding to individual information.
Claims5
A semiconductor testing apparatus, characterized by comprising:
- a first waveform generation unit which generates a common pattern waveform corresponding to common information which is common to each of a plurality of semiconductor devices;
- a plurality of second waveform generation units which generate individual pattern waveforms corresponding to plural pieces of individual information which are prepared individually in association with each of said plurality of semiconductor devices;
- and
- a waveform switching unit which commonly inputs the common pattern generated by said first waveform generation unit and which individually inputs the individual pattern waveforms generated by each of said plurality of second waveform generation units to each of said plurality of semiconductor devices.
A semiconductor testing apparatus, characterized by comprising:
- a first waveform generation unit which generates a common pattern waveform corresponding to common information which is common to each of a plurality of semiconductor devices;
- a plurality of second waveform generation units which generate individual pattern waveforms corresponding to plural pieces of individual information which are prepared individually in association with each of said plurality of semiconductor devices;
- and
- a waveform switching unit which commonly inputs the common pattern generated by said first waveform generation unit and which individually inputs the individual pattern waveforms generated by each of said plurality of second waveform generation units to each of said plurality of semiconductor devices.
Dependencies are inferred from the claim text.