Circuit and method for performing built-in self test and computer readable recording medium for storing program thereof

A built-in self-testing (BIST) method for self-testing a circuit-under-test in a system, wherein the system further comprises a unit circuit having a plurality of input terminals such that the input terminals are coupled to a plurality of signal paths respectively and an output terminal is coupled to the circuit-under-test for providing the circuit-under-test with necessary signals, the BIST method comprising:

• selecting a non-timing-critical path from the signal paths;
• providing a test signal to test the circuit-under-test when the system operates in a test mode;
• and
• switching the selected non-timing-critical path to the test signal so that the test signal can pass through the unit circuit to test the circuit-under-test when the system is in the test mode.

A computer readable recording medium for storing an executable program inside a computer system, the program comprising:

• a function of reading a system including:
• a circuit-under-test;
• and
• a unit circuit having a plurality of input terminals, wherein the input terminals of the unit circuit are coupled to a plurality of signal paths respectively and an output terminal of the unit circuit is coupled to the circuit-under-test for proving the circuit-under-test with necessary signals;
• a function of establishing a built-in self-test (BIST) circuit in the system according the characteristics of the circuit-under-test so that the BIST circuit can provide a self test on the circuit-under-test in the system, wherein the BIST circuit comprises a BIST controller for providing a test signal to test the circuit-under-test when the system operates in a test mode;
• a function of selecting a non-timing-critical path from the signal paths;
• and
• a function of establishing a selection and activation circuit having a plurality of input terminals in the system, wherein one of the input terminals of the selection and activation circuit receives the test signal, another input terminal of the selection and activation circuit is coupled to the selected non-timing-critical path and an output terminal of the selection and activation circuit is coupled to a corresponding input terminal of the unit circuit for outputting the test signal to the output terminal of the selection and activation circuit and then passing the test signal through the unit circuit to test the circuit-under-test when the system operates in the test mode.