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US 7,257,751 B2Granted
Apparatus and method for random pattern built in self-test
OwnerGayvin E Stong, Jeffrey Thomas Robertson +1inventors
InventorsGayvin E Stong, Jeffrey Thomas Robertson, David James Mielke
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Abstract
An apparatus permits built-in self-test (“BIST”) of an IC that includes a memory element having more than one impermissible operation. A code generator accepts a clock signal and generates a test code in response to it. A decoder accepts the test code and generates at least two output lines to disable the impermissible operations during the test. When the decoder is in a decode disabled condition, the output lines reflect a value that permit all possible memory operations.
Claims17
An apparatus comprising:
- a memory element in an integrated circuit, the memory element having at least one deterministic operation and at least one non-deterministic operation controllable by at least two control lines;
- and
- a code generator accepting a seed input and generating a sequence of test codes in response to a clock signal,
- a decoder accepting the test codes and remapping each test code to at least two test enable signals wherein the test enable signals logically combine with the control lines to stimulate only deterministic operations when in a test enabled condition.
1 more element
A built in self test method, comprising:
- providing an integrated circuit having a memory element, the memory element having at least one deterministic operation and at least one non-deterministic operation controllable by at least two control lines;
- generating a sequence of test codes from a seed input in response to a clock signal,
- remapping the test codes to at least two test enable signals, and
- logically combining the test enable signals with the control lines to stimulate only the deterministic operations when in a test enabled condition.
1 more element
Dependencies are inferred from the claim text.