Self-verification of configuration memory in programmable logic devices
AssigneeLattice Semiconductor Corporation
InventorsSatwant Singh, Chi Nguyen, Ann Wu, Ting Yew
Life of this patent
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Abstract
In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.
Claims20
A programmable logic device, comprising:
- a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit;
- a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit;
- a signature calculation engine operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the signature calculation engine calculating during a calculation cycle a signature that includes configuration bits and masking values;
- and
- a comparator operable to compare the signature calculated by the signature calculation engine in a given calculation cycle with a correct signature.
A programmable logic device, comprising:
- a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit;
- a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit;
- an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values;
- and
- a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.
A method for detecting errors in bits stored in a programmable logic device, comprising:
- determining whether a stored bit is a configuration bit or a RAM bit;
- masking the bit if it is determined to be a RAM bit by providing a masking value for the masked RAM bit;
- calculating a signature that includes the configuration bits and the masking values;
- and
- comparing the signature with a correct signature.
Dependencies are inferred from the claim text.