US 7,257,745 B2 · Array self repair using built-in self test techniques

Abstract

A soft-fust test algorithm is distributed on-chip from an ABSIT engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable. Using single-bit MISR error evaluation an ABSIT test sequence is executed concurrently on all arrays through the shift register chain. If any arrays are in error, redundancy compensation is employed and the ABIST test is repeated for all possible array redundant combinations until a functional configuration for each array is identified or all possible redundant combinations have been tried. Once functioning array configurations are verified, the associated soft-fuse states can be used to blow fuses and/or extracted for further system setup, permanent fuse-blowing and yield analysis. Multiple shift register chains driven by separate ABIST engines may be required to test all arrays on a chip.

Claims14

Dependent claims

A method for testing multiple memory arrays that include redundant output lines and are incorporated into integrated circuits comprising:

a) arranging shift register latches in a scan path providing inputs to the arrays and receiving outputs from the arrays;
b) shifting data through the scan path to load the shift register latches with a first data pattern for generating a single bit output for each of the arrays indicating whether one or more of the output lines of the arrays are bad;
c) replacing one of the output lines in any of the arrays indicating a faulty output line with a redundant output line;
d) retesting the arrays using the scan path to see if the output for any of the arrays still indicate at least one bad output line;
e) repeating steps b) to d) until all arrays are good or any bad array cannot be corrected by step c).

2 more elements

A logic system chip having a plurality of memory arrays with redundant memory output lines comprising:

a) an array built in on chip test system for testing said arrays;
b) a scan path linking the multiple arrays to an ABIST generator so that the ABIST generator can provide input signals to each of the arrays and receive output signals from the arrays;
c) a MISR output for each of the arrays arranged in the scan path for the receipt of the output signals from the arrays;
d) a plurality of gate lines linking the outputs of the arrays to the MISR;
and
e) soft fuse output line substitution system responsive to the MISR output for switching the connections of the outputs of the array to the MISR to enable substitution of a redundant output line for any of the output lines.

3 more elements

Dependencies are inferred from the claim text.

Array self repair using built-in self test techniques

Life of this patent

Array self repair using built-in self test techniques

Life of this patent

Abstract

Claims14